nds32: remove .soft_reset_halt dependency
.soft_reset_halt is not necessary for nds32 target. Remove the dependency. Change-Id: Ic3b126d6c7eb995583a661b762627e736222fcaa Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1612 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>__archive__
parent
e8d844a0fd
commit
49d96b1b2e
|
@ -2164,6 +2164,27 @@ int nds32_resume(struct target *target, int current,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static int nds32_soft_reset_halt(struct target *target)
|
||||||
|
{
|
||||||
|
/* TODO: test it */
|
||||||
|
struct nds32 *nds32 = target_to_nds32(target);
|
||||||
|
struct aice_port_s *aice = target_to_aice(target);
|
||||||
|
|
||||||
|
aice_assert_srst(aice, AICE_SRST);
|
||||||
|
|
||||||
|
/* halt core and set pc to 0x0 */
|
||||||
|
int retval = target_halt(target);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
return retval;
|
||||||
|
|
||||||
|
/* start fetching from IVB */
|
||||||
|
uint32_t value_ir3;
|
||||||
|
nds32_get_mapped_reg(nds32, IR3, &value_ir3);
|
||||||
|
nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
int nds32_assert_reset(struct target *target)
|
int nds32_assert_reset(struct target *target)
|
||||||
{
|
{
|
||||||
struct nds32 *nds32 = target_to_nds32(target);
|
struct nds32 *nds32 = target_to_nds32(target);
|
||||||
|
@ -2177,7 +2198,7 @@ int nds32_assert_reset(struct target *target)
|
||||||
&& (cpu_version->revision == 0x1C)
|
&& (cpu_version->revision == 0x1C)
|
||||||
&& (cpu_version->cpu_id_family == 0xC)
|
&& (cpu_version->cpu_id_family == 0xC)
|
||||||
&& (cpu_version->cpu_id_version == 0x0)))
|
&& (cpu_version->cpu_id_version == 0x0)))
|
||||||
target->type->soft_reset_halt(target);
|
nds32_soft_reset_halt(target);
|
||||||
else
|
else
|
||||||
aice_assert_srst(aice, AICE_RESET_HOLD);
|
aice_assert_srst(aice, AICE_RESET_HOLD);
|
||||||
} else {
|
} else {
|
||||||
|
|
|
@ -388,27 +388,6 @@ static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoin
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
static int nds32_v2_soft_reset_halt(struct target *target)
|
|
||||||
{
|
|
||||||
/* TODO: test it */
|
|
||||||
struct nds32 *nds32 = target_to_nds32(target);
|
|
||||||
struct aice_port_s *aice = target_to_aice(target);
|
|
||||||
|
|
||||||
aice_assert_srst(aice, AICE_SRST);
|
|
||||||
|
|
||||||
/* halt core and set pc to 0x0 */
|
|
||||||
int retval = target_halt(target);
|
|
||||||
if (retval != ERROR_OK)
|
|
||||||
return retval;
|
|
||||||
|
|
||||||
/* start fetching from IVB */
|
|
||||||
uint32_t value_ir3;
|
|
||||||
nds32_get_mapped_reg(nds32, IR3, &value_ir3);
|
|
||||||
nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
|
|
||||||
|
|
||||||
return ERROR_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int nds32_v2_deassert_reset(struct target *target)
|
static int nds32_v2_deassert_reset(struct target *target)
|
||||||
{
|
{
|
||||||
int retval;
|
int retval;
|
||||||
|
@ -774,7 +753,6 @@ struct target_type nds32_v2_target = {
|
||||||
|
|
||||||
.assert_reset = nds32_assert_reset,
|
.assert_reset = nds32_assert_reset,
|
||||||
.deassert_reset = nds32_v2_deassert_reset,
|
.deassert_reset = nds32_v2_deassert_reset,
|
||||||
.soft_reset_halt = nds32_v2_soft_reset_halt,
|
|
||||||
|
|
||||||
/* register access */
|
/* register access */
|
||||||
.get_gdb_reg_list = nds32_get_gdb_reg_list,
|
.get_gdb_reg_list = nds32_get_gdb_reg_list,
|
||||||
|
|
|
@ -484,7 +484,6 @@ struct target_type nds32_v3_target = {
|
||||||
|
|
||||||
.assert_reset = nds32_assert_reset,
|
.assert_reset = nds32_assert_reset,
|
||||||
.deassert_reset = nds32_v3_deassert_reset,
|
.deassert_reset = nds32_v3_deassert_reset,
|
||||||
.soft_reset_halt = nds32_v3_soft_reset_halt,
|
|
||||||
|
|
||||||
/* register access */
|
/* register access */
|
||||||
.get_gdb_reg_list = nds32_get_gdb_reg_list,
|
.get_gdb_reg_list = nds32_get_gdb_reg_list,
|
||||||
|
|
|
@ -369,12 +369,6 @@ int nds32_v3_target_request_data(struct target *target,
|
||||||
return ERROR_OK;
|
return ERROR_OK;
|
||||||
}
|
}
|
||||||
|
|
||||||
int nds32_v3_soft_reset_halt(struct target *target)
|
|
||||||
{
|
|
||||||
struct aice_port_s *aice = target_to_aice(target);
|
|
||||||
return aice_assert_srst(aice, AICE_RESET_HOLD);
|
|
||||||
}
|
|
||||||
|
|
||||||
int nds32_v3_checksum_memory(struct target *target,
|
int nds32_v3_checksum_memory(struct target *target,
|
||||||
uint32_t address, uint32_t count, uint32_t *checksum)
|
uint32_t address, uint32_t count, uint32_t *checksum)
|
||||||
{
|
{
|
||||||
|
|
|
@ -34,7 +34,6 @@ struct nds32_v3_common_callback {
|
||||||
void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback);
|
void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback);
|
||||||
int nds32_v3_target_request_data(struct target *target,
|
int nds32_v3_target_request_data(struct target *target,
|
||||||
uint32_t size, uint8_t *buffer);
|
uint32_t size, uint8_t *buffer);
|
||||||
int nds32_v3_soft_reset_halt(struct target *target);
|
|
||||||
int nds32_v3_checksum_memory(struct target *target,
|
int nds32_v3_checksum_memory(struct target *target,
|
||||||
uint32_t address, uint32_t count, uint32_t *checksum);
|
uint32_t address, uint32_t count, uint32_t *checksum);
|
||||||
int nds32_v3_hit_watchpoint(struct target *target,
|
int nds32_v3_hit_watchpoint(struct target *target,
|
||||||
|
|
|
@ -473,7 +473,6 @@ struct target_type nds32_v3m_target = {
|
||||||
|
|
||||||
.assert_reset = nds32_assert_reset,
|
.assert_reset = nds32_assert_reset,
|
||||||
.deassert_reset = nds32_v3m_deassert_reset,
|
.deassert_reset = nds32_v3m_deassert_reset,
|
||||||
.soft_reset_halt = nds32_v3_soft_reset_halt,
|
|
||||||
|
|
||||||
/* register access */
|
/* register access */
|
||||||
.get_gdb_reg_list = nds32_get_gdb_reg_list,
|
.get_gdb_reg_list = nds32_get_gdb_reg_list,
|
||||||
|
|
Loading…
Reference in New Issue