David Brownell <david-b@pacbell.net>:
Update docs for most of the remaining commands in jtag.c: - switch to @deffn - these are just the "low level" JTAG commands - resolve much goofage! * remove docs for non-existent commands * add missing docs for some existing commands * fix incorrect docs for some commands - just index TAP states overall, not individually - current name is "RUN/IDLE" not "IDLE" Cross checked against the source. This also creates an "Interface Drivers" section, analagous to how (NOR) Flash and NAND drivers are presented; that's not yet sorted. git-svn-id: svn://svn.berlios.de/openocd/trunk@2014 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
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doc/openocd.texi
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doc/openocd.texi
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@ -1335,18 +1335,25 @@ jtag_speed 0
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@verbatim
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interface arm-jtag-ew
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@end verbatim
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@section Interface Command
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@section Interface Configuration
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The interface command tells OpenOCD what type of JTAG dongle you are
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using. Depending on the type of dongle, you may need to have one or
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more additional commands.
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@itemize @bullet
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@deffn {Config Command} {interface} name
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Use the interface driver @var{name} to connect to the
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target.
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@end deffn
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@item @b{interface} <@var{name}>
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@cindex interface
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@*Use the interface driver <@var{name}> to connect to the
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target. Currently supported interfaces are
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@deffn Command {jtag interface}
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Returns the name of the interface driver being used.
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@end deffn
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@section Interface Drivers
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Currently supported interface drivers are:
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@itemize @minus
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@ -1386,10 +1393,8 @@ libusb.
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@item @b{arm-jtag-ew}
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@* Olimex ARM-JTAG-EW USB adapter
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@comment - End parameters
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@end itemize
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@comment - End Interface
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@end itemize
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@subsection parport options
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@itemize @bullet
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@ -1523,10 +1528,6 @@ also reduces the risk of timeouts before receiving the expected number of bytes.
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The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
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@end itemize
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@subsection ep93xx options
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@cindex ep93xx options
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Currently, there are no options available for the ep93xx interface.
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@anchor{JTAG Speed}
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@section JTAG Speed
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JTAG clock setup is part of system setup.
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@ -1646,7 +1647,7 @@ and @command{reset init} commands; after @command{reset init} a
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board-specific script might do things like setting up DRAM.
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(@xref{Reset Command}.)
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@section SRST and TRST Signal Issues
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@section SRST and TRST Issues
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Because SRST and TRST are hardware signals, they can have a
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variety of system-specific constraints. Some of the most
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@ -1685,6 +1686,15 @@ Also, with weak pullups it may be advisable to drive
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signals to both levels (push/pull) to minimize rise times.
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Use the @command{reset_config} @var{trst_type} and
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@var{srst_type} parameters to say how to drive reset signals.
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@item @emph{Special initialization} ... Targets sometimes need
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special JTAG initialization sequences to handle chip-specific
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issues (not limited to errata).
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For example, certain JTAG commands might need to be issued while
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the system as a whole is in a reset state (SRST active)
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but the JTAG scan chain is usable (TRST inactive).
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(@xref{JTAG Commands}, where the @command{jtag_reset}
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command is presented.)
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@end itemize
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There can also be other issues.
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@ -4236,87 +4246,203 @@ otherwise the libdcc format is used.
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@node JTAG Commands
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@chapter JTAG Commands
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@cindex JTAG Commands
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Generally most people will not use the bulk of these commands. They
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are mostly used by the OpenOCD developers or those who need to
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directly manipulate the JTAG taps.
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Most general purpose JTAG commands have been presented earlier.
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(@xref{JTAG Speed}, @ref{Reset Configuration}, and @ref{TAP Creation}.)
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Lower level JTAG commands, as presented here,
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may be needed to work with targets which require special
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attention during operations such as reset or initialization.
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To use these commands you will need to understand some
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of the basics of JTAG, including:
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In general these commands control JTAG taps at a very low level. For
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example if you need to control a JTAG Route Controller (i.e.: the
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OMAP3530 on the Beagle Board has one) you might use these commands in
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a script or an event procedure.
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@section Commands
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@cindex Commands
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@itemize @bullet
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@item @b{scan_chain}
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@cindex scan_chain
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@*Print current scan chain configuration.
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@item @b{jtag_reset} <@var{trst}> <@var{srst}>
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@cindex jtag_reset
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@*Toggle reset lines.
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@item @b{endstate} <@var{tap_state}>
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@cindex endstate
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@*Finish JTAG operations in <@var{tap_state}>.
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@item @b{runtest} <@var{num_cycles}>
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@cindex runtest
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@*Move to Run-Test/Idle, and execute <@var{num_cycles}>
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@item @b{statemove} [@var{tap_state}]
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@cindex statemove
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@*Move to current endstate or [@var{tap_state}]
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@item @b{irscan} <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
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@cindex irscan
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@*Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
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@item @b{drscan} <@var{device}> [@var{dev2}] [@var{var2}] ...
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@cindex drscan
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@*Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
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@item @b{verify_ircapture} <@option{enable}|@option{disable}>
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@cindex verify_ircapture
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@*Verify value captured during Capture-IR. Default is enabled.
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@item @b{var} <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
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@cindex var
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@*Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
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@item @b{field} <@var{var}> <@var{field}> [@var{value}|@var{flip}]
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@cindex field
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Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}].
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@item A JTAG scan chain consists of a sequence of individual TAP
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devices such as a CPUs.
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@item Control operations involve moving each TAP through the same
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standard state machine (in parallel)
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using their shared TMS and clock signals.
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@item Data transfer involves shifting data through the chain of
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instruction or data registers of each TAP, writing new register values
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while the reading previous ones.
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@item Data register sizes are a function of the instruction active in
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a given TAP, while instruction register sizes are fixed for each TAP.
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All TAPs support a BYPASS instruction with a single bit data register.
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@item The way OpenOCD differentiates between TAP devices is by
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shifting different instructions into (and out of) their instruction
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registers.
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@end itemize
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@section Tap states
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@cindex Tap states
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Available tap_states are:
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@section Low Level JTAG Commands
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These commands are used by developers who need to access
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JTAG instruction or data registers, possibly controlling
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the order of TAP state transitions.
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If you're not debugging OpenOCD internals, or bringing up a
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new JTAG adapter or a new type of TAP device (like a CPU or
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JTAG router), you probably won't need to use these commands.
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@deffn Command {drscan} tap [numbits value]+ [@option{-endstate} tap_state]
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Loads the data register of @var{tap} with a series of bit fields
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that specify the entire register.
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Each field is @var{numbits} bits long with
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a numeric @var{value} (hexadecimal encouraged).
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The return value holds the original value of each
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of those fields.
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For example, a 38 bit number might be specified as one
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field of 32 bits then one of 6 bits.
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@emph{For portability, never pass fields which are more
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than 32 bits long. Many OpenOCD implementations do not
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support 64-bit (or larger) integer values.}
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All TAPs other than @var{tap} must be in BYPASS mode.
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The single bit in their data registers does not matter.
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When @var{tap_state} is specified, the JTAG state machine is left
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in that state.
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For example @sc{drpause} might be specified, so that more
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instructions can be issued before re-entering the @sc{run/idle} state.
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If the end state is not specified, the @sc{run/idle} state is entered.
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@quotation Warning
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OpenOCD does not record information about data register lengths,
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so @emph{it is important that you get the bit field lengths right}.
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Remember that different JTAG instructions refer to different
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data registers, which may have different lengths.
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Moreover, those lengths may not be fixed;
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the SCAN_N instruction can change the length of
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the register accessed by the INTEST instruction
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(by connecting a different scan chain).
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@end quotation
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@end deffn
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@deffn Command {flush_count}
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Returns the number of times the JTAG queue has been flushed.
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This may be used for performance tuning.
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For example, flushing a queue over USB involves a
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minimum latency, often several milliseconds, which does
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not change with the amount of data which is written.
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You may be able to identify performance problems by finding
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tasks which waste bandwidth by flushing small transfers too often,
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instead of batching them into larger operations.
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@end deffn
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@deffn Command {endstate} tap_state
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Flush any pending JTAG operations,
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and return with all TAPs in @var{tap_state}.
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This state should be a stable state such as @sc{reset},
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@sc{run/idle},
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@sc{drpause}, or @sc{irpause}.
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@end deffn
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@deffn Command {irscan} [tap instruction]+ [@option{-endstate} tap_state]
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For each @var{tap} listed, loads the instruction register
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with its associated numeric @var{instruction}.
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(The number of bits in that instruction may be displayed
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using the @command{scan_chain} command.)
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For other TAPs, a BYPASS instruction is loaded.
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When @var{tap_state} is specified, the JTAG state machine is left
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in that state.
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For example @sc{irpause} might be specified, so the data register
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can be loaded before re-entering the @sc{run/idle} state.
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If the end state is not specified, the @sc{run/idle} state is entered.
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@quotation Note
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OpenOCD currently supports only a single field for instruction
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register values, unlike data register values.
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For TAPs where the instruction register length is more than 32 bits,
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portable scripts currently must issue only BYPASS instructions.
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@end quotation
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@end deffn
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@deffn Command {jtag_reset} trst srst
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Set values of reset signals.
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The @var{trst} and @var{srst} parameter values may be
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@option{0}, indicating that reset is inactive (pulled or driven high),
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or @option{1}, indicating it is active (pulled or driven low).
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The @command{reset_config} command should already have been used
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to configure how the board and JTAG adapter treat these two
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signals, and to say if either signal is even present.
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@xref{Reset Configuration}.
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@end deffn
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@deffn Command {runtest} @var{num_cycles}
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Move to the @sc{run/idle} state, and execute at least
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@var{num_cycles} of the JTAG clock (TCK).
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Instructions often need some time
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to execute before they take effect.
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@end deffn
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@deffn Command {scan_chain}
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Displays the TAPs in the scan chain configuration,
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and their status.
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The set of TAPs listed by this command is fixed by
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exiting the OpenOCD configuration stage,
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but systems with a JTAG router can
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enable or disable TAPs dynamically.
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In addition to the enable/disable status, the contents of
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each TAP's instruction register can also change.
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@end deffn
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@c tms_sequence (short|long)
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@c ... temporary, debug-only, probably gone before 0.2 ships
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@deffn Command {verify_ircapture} (@option{enable}|@option{disable})
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Verify values captured during @sc{ircapture} and returned
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during IR scans. Default is enabled, but this can be
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overridden by @command{verify_jtag}.
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@end deffn
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@deffn Command {verify_jtag} (@option{enable}|@option{disable})
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Enables verification of DR and IR scans, to help detect
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programming errors. For IR scans, @command{verify_ircapture}
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must also be enabled.
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Default is enabled.
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@end deffn
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@section TAP state names
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@cindex TAP state names
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The @var{tap_state} names used by OpenOCD in the @command{drscan},
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@command{endstate}, and @command{irscan} commands are:
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@itemize @bullet
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@item @b{RESET}
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@cindex RESET
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@item @b{IDLE}
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@cindex IDLE
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@item @b{RUN/IDLE}
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@item @b{DRSELECT}
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@cindex DRSELECT
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@item @b{DRCAPTURE}
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@cindex DRCAPTURE
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@item @b{DRSHIFT}
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@cindex DRSHIFT
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@item @b{DREXIT1}
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@cindex DREXIT1
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@item @b{DRPAUSE}
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@cindex DRPAUSE
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@item @b{DREXIT2}
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@cindex DREXIT2
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@item @b{DRUPDATE}
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@cindex DRUPDATE
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@item @b{IRSELECT}
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@cindex IRSELECT
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@item @b{IRCAPTURE}
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@cindex IRCAPTURE
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@item @b{IRSHIFT}
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@cindex IRSHIFT
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@item @b{IREXIT1}
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@cindex IREXIT1
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@item @b{IRPAUSE}
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@cindex IRPAUSE
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@item @b{IREXIT2}
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@cindex IREXIT2
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@item @b{IRUPDATE}
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@cindex IRUPDATE
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@end itemize
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Note that only six of those states are fully ``stable'' in the
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face of TMS fixed and a free-running JTAG clock; for all the
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others, the next TCK transition changes to a new state.
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@itemize @bullet
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@item @sc{reset} is probably most useful with @command{endstate},
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but entering it frequently has side effects.
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(This is the only stable state with TMS high.)
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@item From @sc{drshift} and @sc{irshift}, clock transitions will
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produce side effects by changing register contents. The values
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to be latched in upcoming @sc{drupdate} or @sc{irupdate} states
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may not be as expected.
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@item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
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choices after @command{drscan} or @command{irscan} commands,
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since they are free of side effects.
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@end itemize
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@node TFTP
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@chapter TFTP
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