Figure out Debug RAM size in examine().
It compiles, so that means it works, right?__archive__
Tim Newsome
parent
48cf8eebf1
commit
495384e15f
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@ -1,17 +1,168 @@
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#include <assert.h>
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "target.h"
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#include "target_type.h"
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#include "log.h"
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#include "jtag/jtag.h"
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static int riscv_poll(struct target *target)
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#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
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#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
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/*** JTAG registers. ***/
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#define DTMINFO 0x10
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#define DTMINFO_ADDRBITS (0xf<<4)
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#define DTMINFO_VERSION (0xf)
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#define DBUS 0x11
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/*** Debug Bus registers. ***/
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#define DMCONTROL 0x10
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#define DMCONTROL_HALTNOT (1<<33)
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#define DMCONTROL_INTERRUPT (1<<32)
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#define DMCONTROL_BUSERROR (7<<19)
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#define DMCONTROL_SERIAL (3<<16)
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#define DMCONTROL_AUTOINCREMENT (1<<15)
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#define DMCONTROL_ACCESS (7<<12)
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#define DMCONTROL_HARTID (0x3ff<<2)
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#define DMCONTROL_NDRESET (1<<1)
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#define DMCONTROL_FULLRESET 1
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#define DMINFO 0x11
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#define DMINFO_ABUSSIZE (0x7f<<25)
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#define DMINFO_SERIALCOUNT (0xf<<21)
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#define DMINFO_ACCESS128 (1<<20)
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#define DMINFO_ACCESS64 (1<<19)
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#define DMINFO_ACCESS32 (1<<18)
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#define DMINFO_ACCESS16 (1<<17)
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#define DMINFO_ACCESS8 (1<<16)
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#define DMINFO_DRAMSIZE (0x3f<<10)
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#define DMINFO_AUTHENTICATED (1<<5)
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#define DMINFO_AUTHBUSY (1<<4)
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#define DMINFO_AUTHTYPE (3<<2)
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#define DMINFO_VERSION 3
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/*** Info about the core being debugged. ***/
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#define DBUS_ADDRESS_UNKNOWN 0xffff
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typedef struct {
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/* Number of address bits in the dbus register. */
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uint8_t addrbits;
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/* Width of a GPR (and many other things) in bits. */
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uint8_t xlen;
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/* Last value we wrote to DBUS_ADDRESS (eg. the address of the register
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* whose value will be read the next time we scan dbus). */
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uint16_t dbus_address;
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/* Number of words in Debug RAM. */
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unsigned int dramsize;
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} riscv_info_t;
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static uint64_t dbus_scan(struct target *target, uint16_t address,
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uint64_t data_out, bool read, bool write)
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{
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return 0;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct scan_field field;
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uint8_t in[8];
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uint8_t out[8];
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assert(info->addrbits != 0);
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// TODO: max bits is 32?
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field.num_bits = info->addrbits + 35;
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field.out_value = out;
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if (read) {
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field.in_value = in;
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}
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buf_set_u64(out, 0, 34, data_out);
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buf_set_u64(out, 34, info->addrbits, address);
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buf_set_u64(out, info->addrbits + 34, 1, write);
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/* Assume dbus is already selected. */
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jtag_add_dr_scan(target->tap, 1, &field, TAP_DRUPDATE);
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info->dbus_address = address;
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return buf_get_u64(in, 0, 34);
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}
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static uint64_t dbus_read(struct target *target, uint16_t address, uint16_t next_address)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (address != info->dbus_address) {
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dbus_scan(target, address, 0, false, false);
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}
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return dbus_scan(target, next_address, 0, true, false);
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}
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static uint32_t dtminfo_read(struct target *target)
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{
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struct scan_field field;
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uint8_t in[4];
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uint8_t out[4];
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field.num_bits = target->tap->ir_length;
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field.out_value = out;
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field.in_value = NULL;
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buf_set_u32(out, 0, field.num_bits, DTMINFO);
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jtag_add_ir_scan(target->tap, &field, TAP_DRSELECT);
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field.num_bits = 32;
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field.out_value = NULL;
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field.in_value = in;
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jtag_add_dr_scan(target->tap, 1, &field, TAP_DRUPDATE);
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/* Always return to dbus. */
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/* TODO: Can we rely on IR not being messed with between calls into
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* RISCV code? Eg. what happens if there are multiple cores and some
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* other core is accessed? */
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field.num_bits = target->tap->ir_length;
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field.out_value = out;
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field.in_value = NULL;
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buf_set_u32(out, 0, field.num_bits, DBUS);
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jtag_add_ir_scan(target->tap, &field, TAP_DRSELECT);
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return buf_get_u32(field.in_value, 0, 32);
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}
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static int riscv_init_target(struct command_context *cmd_ctx,
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struct target *target)
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{
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target->arch_info = calloc(1, sizeof(riscv_info_t));
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->dbus_address = DBUS_ADDRESS_UNKNOWN;
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return ERROR_OK;
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}
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int riscv_examine(struct target *target)
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{
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if (target_was_examined(target)) {
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return ERROR_OK;
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}
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uint32_t dtminfo = dtminfo_read(target);
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->addrbits = get_field(dtminfo, DTMINFO_ADDRBITS);
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/* TODO: Figure out size of debug RAM, and allocate it. */
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uint64_t dminfo = dbus_read(target, DMINFO, 0);
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info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
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target_set_examined(target);
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return ERROR_OK;
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}
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struct target_type riscv_target = {
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.name = "riscv",
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.poll = riscv_poll,
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.init_target = riscv_init_target,
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.examine = riscv_examine,
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};
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