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mips: optimize mips_ejtag_step_disable() code 

The code is a bit large compared to mips_ejtag_step_enable().
With the mips32 xori instruction the code can be
reused.
The number of pracc accesses are reduced from 18 to 7.

Change-Id: If3974ebd64da4461c22b089796646990e68e1b72
Signed-off-by: Salvador Arroyo <sarroyofdez@yahoo.es>
Reviewed-on: http://openocd.zylin.com/944
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
__archive__
Salvador Arroyo 2012-10-30 23:15:35 +01:00 committed by Spencer Oliver
parent 115b7be426
commit 47d5f44fe0
2 changed files with 26 additions and 41 deletions
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2
src/target/mips32.h
View File

@ -144,6 +144,7 @@ struct mips32_algorithm {
#define MIPS32_OP_SH 0x29
#define MIPS32_OP_SW 0x2B
#define MIPS32_OP_ORI 0x0D
#define MIPS32_OP_XORI 0x0E
#define MIPS32_OP_XOR 0x26
#define MIPS32_OP_SLTU 0x2B
#define MIPS32_OP_SRL 0x03
@ -186,6 +187,7 @@ struct mips32_algorithm {
#define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
#define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
#define MIPS32_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
#define MIPS32_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
#define MIPS32_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
#define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
#define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)

65
src/target/mips_ejtag.c
View File

@ -190,49 +190,32 @@ void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data)
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
}
static int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
{
static const uint32_t code[] = {
MIPS32_MTC0(1, 31, 0), /* move $1 to COP0 DeSave */
MIPS32_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
MIPS32_ORI(1, 1, 0x0100), /* set SSt bit in debug reg */
MIPS32_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
MIPS32_B(NEG16(5)),
MIPS32_MFC0(1, 31, 0), /* move COP0 DeSave to $1 */
};
return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
0, NULL, 0, NULL, 1);
}
static int mips_ejtag_step_disable(struct mips_ejtag *ejtag_info)
{
static const uint32_t code[] = {
MIPS32_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
MIPS32_LUI(15, UPPER16(MIPS32_PRACC_STACK)), /* $15 = MIPS32_PRACC_STACK */
MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_STACK)),
MIPS32_SW(1, 0, 15), /* sw $1,($15) */
MIPS32_SW(2, 0, 15), /* sw $2,($15) */
MIPS32_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
MIPS32_LUI(2, 0xFFFF), /* $2 = 0xfffffeff */
MIPS32_ORI(2, 2, 0xFEFF),
MIPS32_AND(1, 1, 2),
MIPS32_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
MIPS32_LW(2, 0, 15),
MIPS32_LW(1, 0, 15),
MIPS32_B(NEG16(13)),
MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
};
return mips32_pracc_exec(ejtag_info, ARRAY_SIZE(code), code,
0, NULL, 0, NULL, 1);
}
/* Set (to enable) or clear (to disable stepping) the SSt bit (bit 8) in Cp0 Debug reg (reg 23, sel 0) */
int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
{
if (enable_step)
return mips_ejtag_step_enable(ejtag_info);
return mips_ejtag_step_disable(ejtag_info);
int code_len = enable_step ? 6 : 7;
uint32_t *code = malloc(code_len * sizeof(uint32_t));
if (code == NULL) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
}
uint32_t *code_p = code;
*code_p++ = MIPS32_MTC0(1, 31, 0); /* move $1 to COP0 DeSave */
*code_p++ = MIPS32_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
*code_p++ = MIPS32_ORI(1, 1, 0x0100); /* set SSt bit in debug reg */
if (!enable_step)
*code_p++ = MIPS32_XORI(1, 1, 0x0100); /* clear SSt bit in debug reg */
*code_p++ = MIPS32_MTC0(1, 23, 0); /* move $1 to COP0 Debug */
*code_p++ = MIPS32_B(NEG16((code_len - 1))); /* jump to start */
*code_p = MIPS32_MFC0(1, 31, 0); /* move COP0 DeSave to $1 */
int retval = mips32_pracc_exec(ejtag_info, code_len, code, 0, NULL, 0, NULL, 1);
free(code);
return retval;
}
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)