cortex_a8: remove dap_ap_sel calls
add new mem_ap_sel_* functions (as was made for cortex_a9)
see commit: 779005f43d
Signed-off-by: Luca Ellero <lroluk@gmail.com>
__archive__
Luca Ellero
Øyvind Harboe
parent
f26cd96740
commit
47b5829db4
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@ -81,7 +81,6 @@ static int cortex_a8_init_debug_access(struct target *target)
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{
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = &armv7a->dap;
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int retval;
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uint32_t dummy;
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@ -89,11 +88,13 @@ static int cortex_a8_init_debug_access(struct target *target)
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/* Unlocking the debug registers for modification */
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/* The debugport might be uninitialised so try twice */
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retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
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retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
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if (retval != ERROR_OK)
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{
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/* try again */
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retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
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retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
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if (retval == ERROR_OK)
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{
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LOG_USER("Locking debug access failed on first, but succeeded on second try.");
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@ -103,7 +104,8 @@ static int cortex_a8_init_debug_access(struct target *target)
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return retval;
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/* Clear Sticky Power Down status Bit in PRSR to enable access to
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the registers in the Core Power Domain */
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retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_PRSR, &dummy);
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if (retval != ERROR_OK)
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return retval;
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@ -112,9 +114,7 @@ static int cortex_a8_init_debug_access(struct target *target)
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/* Resync breakpoint registers */
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/* Since this is likely called from init or reset, update target state information*/
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retval = cortex_a8_poll(target);
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return retval;
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return cortex_a8_poll(target);
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}
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/* To reduce needless round-trips, pass in a pointer to the current
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@ -138,7 +138,7 @@ static int cortex_a8_exec_opcode(struct target *target,
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long long then = timeval_ms();
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while ((dscr & DSCR_INSTR_COMP) == 0)
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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{
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@ -152,14 +152,15 @@ static int cortex_a8_exec_opcode(struct target *target,
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}
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}
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retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
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retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_ITR, opcode);
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if (retval != ERROR_OK)
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return retval;
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then = timeval_ms();
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do
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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{
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@ -201,11 +202,8 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre
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if (retval != ERROR_OK)
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return retval;
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dap_ap_select(swjdp, swjdp_memoryap);
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retval = mem_ap_read_buf_u32(swjdp, (uint8_t *)(®file[1]), 4*15, address);
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if (retval != ERROR_OK)
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return retval;
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dap_ap_select(swjdp, swjdp_debugap);
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retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap,
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(uint8_t *)(®file[1]), 4*15, address);
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return retval;
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}
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@ -262,7 +260,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
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long long then = timeval_ms();
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while ((dscr & DSCR_DTR_TX_FULL) == 0)
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -273,7 +271,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target,
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}
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}
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DTRTX, value);
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LOG_DEBUG("read DCC 0x%08" PRIx32, *value);
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@ -292,7 +290,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
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LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
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/* Check that DCCRX is not full */
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -311,7 +309,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
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/* Write DTRRX ... sets DSCR.DTRRXfull but exec_opcode() won't care */
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LOG_DEBUG("write DCC 0x%08" PRIx32, value);
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retval = mem_ap_write_u32(swjdp,
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retval = mem_ap_sel_write_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DTRRX, value);
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if (retval != ERROR_OK)
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return retval;
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@ -372,7 +370,7 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = &armv7a->dap;
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retval = mem_ap_write_atomic_u32(swjdp, address, value);
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retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value);
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return retval;
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}
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@ -396,7 +394,7 @@ static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
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static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
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{
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LOG_DEBUG("write DCC 0x%08" PRIx32, data);
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return mem_ap_write_u32(&a8->armv7a_common.dap,
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return mem_ap_sel_write_u32(&a8->armv7a_common.dap, swjdp_debugap,
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a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
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}
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@ -413,7 +411,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
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/* Wait for DTRRXfull */
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long long then = timeval_ms();
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while ((dscr & DSCR_DTR_TX_FULL) == 0) {
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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a8->armv7a_common.debug_base + CPUDBG_DSCR,
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&dscr);
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if (retval != ERROR_OK)
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@ -425,7 +423,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
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}
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}
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
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if (retval != ERROR_OK)
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return retval;
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@ -448,7 +446,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
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long long then = timeval_ms();
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for (;;)
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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a8->armv7a_common.debug_base + CPUDBG_DSCR,
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&dscr);
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if (retval != ERROR_OK)
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@ -685,14 +683,11 @@ static int cortex_a8_poll(struct target *target)
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struct armv7a_common *armv7a = &cortex_a8->armv7a_common;
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struct adiv5_dap *swjdp = &armv7a->dap;
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enum target_state prev_target_state = target->state;
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uint8_t saved_apsel = dap_ap_get_select(swjdp);
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dap_ap_select(swjdp, swjdp_debugap);
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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{
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dap_ap_select(swjdp, saved_apsel);
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return retval;
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}
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cortex_a8->cpudbg_dscr = dscr;
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@ -737,8 +732,6 @@ static int cortex_a8_poll(struct target *target)
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target->state = TARGET_UNKNOWN;
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}
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dap_ap_select(swjdp, saved_apsel);
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return retval;
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}
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@ -748,37 +741,36 @@ static int cortex_a8_halt(struct target *target)
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uint32_t dscr;
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struct armv7a_common *armv7a = target_to_armv7a(target);
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struct adiv5_dap *swjdp = &armv7a->dap;
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uint8_t saved_apsel = dap_ap_get_select(swjdp);
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dap_ap_select(swjdp, swjdp_debugap);
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/*
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* Tell the core to be halted by writing DRCR with 0x1
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* and then wait for the core to be halted.
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*/
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retval = mem_ap_write_atomic_u32(swjdp,
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retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DRCR, 0x1);
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if (retval != ERROR_OK)
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goto out;
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return retval;
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/*
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* enter halting debug mode
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*/
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retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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goto out;
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return retval;
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retval = mem_ap_write_atomic_u32(swjdp,
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retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, dscr | DSCR_HALT_DBG_MODE);
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if (retval != ERROR_OK)
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goto out;
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return retval;
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long long then = timeval_ms();
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for (;;)
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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goto out;
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return retval;
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if ((dscr & DSCR_CORE_HALTED) != 0)
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{
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break;
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@ -792,9 +784,7 @@ static int cortex_a8_halt(struct target *target)
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target->debug_reason = DBG_REASON_DBGRQ;
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out:
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dap_ap_select(swjdp, saved_apsel);
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return retval;
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return ERROR_OK;
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}
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static int cortex_a8_resume(struct target *target, int current,
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@ -808,9 +798,6 @@ static int cortex_a8_resume(struct target *target, int current,
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// struct breakpoint *breakpoint = NULL;
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uint32_t resume_pc, dscr;
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uint8_t saved_apsel = dap_ap_get_select(swjdp);
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dap_ap_select(swjdp, swjdp_debugap);
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if (!debug_execution)
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target_free_all_working_areas(target);
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@ -889,14 +876,15 @@ static int cortex_a8_resume(struct target *target, int current,
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* REVISIT: for single stepping, we probably want to
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* disable IRQs by default, with optional override...
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*/
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retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
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retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DRCR, 0x2);
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if (retval != ERROR_OK)
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return retval;
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long long then = timeval_ms();
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for (;;)
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -928,8 +916,6 @@ static int cortex_a8_resume(struct target *target, int current,
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LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
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}
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dap_ap_select(swjdp, saved_apsel);
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return ERROR_OK;
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}
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@ -948,7 +934,7 @@ static int cortex_a8_debug_entry(struct target *target)
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LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
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/* REVISIT surely we should not re-read DSCR !! */
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -960,7 +946,7 @@ static int cortex_a8_debug_entry(struct target *target)
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/* Enable the ITR execution once we are in debug mode */
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dscr |= DSCR_ITR_EN;
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retval = mem_ap_write_atomic_u32(swjdp,
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retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_DSCR, dscr);
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if (retval != ERROR_OK)
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return retval;
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@ -972,7 +958,7 @@ static int cortex_a8_debug_entry(struct target *target)
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if (target->debug_reason == DBG_REASON_WATCHPOINT) {
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uint32_t wfar;
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retval = mem_ap_read_atomic_u32(swjdp,
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retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
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armv7a->debug_base + CPUDBG_WFAR,
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&wfar);
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if (retval != ERROR_OK)
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@ -993,10 +979,9 @@ static int cortex_a8_debug_entry(struct target *target)
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}
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else
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{
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dap_ap_select(swjdp, swjdp_memoryap);
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retval = cortex_a8_read_regs_through_mem(target,
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regfile_working_area->address, regfile);
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dap_ap_select(swjdp, swjdp_memoryap);
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target_free_working_area(target, regfile_working_area);
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if (retval != ERROR_OK)
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{
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@ -1007,7 +992,7 @@ static int cortex_a8_debug_entry(struct target *target)
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retval = cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
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if (retval != ERROR_OK)
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return retval;
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dap_ap_select(swjdp, swjdp_debugap);
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LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
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arm_set_cpsr(armv4_5, cpsr);
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@ -1469,13 +1454,16 @@ static int cortex_a8_read_phys_memory(struct target *target,
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if (count && buffer) {
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switch (size) {
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case 4:
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retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
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retval = mem_ap_sel_read_buf_u32(swjdp, swjdp_memoryap,
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buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
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retval = mem_ap_sel_read_buf_u16(swjdp, swjdp_memoryap,
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buffer, 2 * count, address);
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break;
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case 1:
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retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
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retval = mem_ap_sel_read_buf_u8(swjdp, swjdp_memoryap,
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buffer, count, address);
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break;
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}
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}
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@ -1526,13 +1514,16 @@ static int cortex_a8_write_phys_memory(struct target *target,
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if (count && buffer) {
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switch (size) {
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case 4:
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retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
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retval = mem_ap_sel_write_buf_u32(swjdp, swjdp_memoryap,
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buffer, 4 * count, address);
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break;
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case 2:
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retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
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||||
retval = mem_ap_sel_write_buf_u16(swjdp, swjdp_memoryap,
|
||||
buffer, 2 * count, address);
|
||||
break;
|
||||
case 1:
|
||||
retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
|
||||
retval = mem_ap_sel_write_buf_u8(swjdp, swjdp_memoryap,
|
||||
buffer, count, address);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -1610,6 +1601,7 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address,
|
|||
retval = cortex_a8_mmu(target, &enabled);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if(enabled)
|
||||
{
|
||||
virt = address;
|
||||
|
|
@ -1630,7 +1622,6 @@ static int cortex_a8_bulk_write_memory(struct target *target, uint32_t address,
|
|||
return cortex_a8_write_memory(target, address, 4, count, buffer);
|
||||
}
|
||||
|
||||
|
||||
static int cortex_a8_dcc_read(struct adiv5_dap *swjdp, uint8_t *value, uint8_t *ctrl)
|
||||
{
|
||||
#if 0
|
||||
|
|
@ -1733,32 +1724,33 @@ static int cortex_a8_examine_first(struct target *target)
|
|||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
|
||||
retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
|
||||
armv7a->debug_base + CPUDBG_CPUID, &cpuid);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
if ((retval = mem_ap_read_atomic_u32(swjdp,
|
||||
if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
|
||||
armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
|
||||
{
|
||||
LOG_DEBUG("Examine %s failed", "CPUID");
|
||||
return retval;
|
||||
}
|
||||
|
||||
if ((retval = mem_ap_read_atomic_u32(swjdp,
|
||||
if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
|
||||
armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
|
||||
{
|
||||
LOG_DEBUG("Examine %s failed", "CTYPR");
|
||||
return retval;
|
||||
}
|
||||
|
||||
if ((retval = mem_ap_read_atomic_u32(swjdp,
|
||||
if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
|
||||
armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
|
||||
{
|
||||
LOG_DEBUG("Examine %s failed", "TTYPR");
|
||||
return retval;
|
||||
}
|
||||
|
||||
if ((retval = mem_ap_read_atomic_u32(swjdp,
|
||||
if ((retval = mem_ap_sel_read_atomic_u32(swjdp, swjdp_debugap,
|
||||
armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
|
||||
{
|
||||
LOG_DEBUG("Examine %s failed", "DIDR");
|
||||
|
|
|
|||
Loading…
Reference in New Issue