Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASE
git-svn-id: svn://svn.berlios.de/openocd/trunk@2716 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
mlu
parent
9542318312
commit
45f03dd9b5
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@ -163,18 +163,18 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
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do
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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}
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while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
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mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
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mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
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do
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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}
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@ -221,7 +221,7 @@ int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
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/* Read DCCTX */
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retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
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armv7a->debug_base + CPUDBG_DTRTX, value);
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return retval;
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}
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@ -236,7 +236,7 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
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swjdp_common_t *swjdp = &armv7a->swjdp_info;
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retval = mem_ap_write_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
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armv7a->debug_base + CPUDBG_DTRRX, value);
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/* Move DTRRX to r0 */
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cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
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@ -291,12 +291,12 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
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do
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{
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retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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}
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while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
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retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
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armv7a->debug_base + CPUDBG_DTRTX, value);
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return retval;
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}
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@ -316,7 +316,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
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/* Write to DCCRX */
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retval = mem_ap_write_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
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armv7a->debug_base + CPUDBG_DTRRX, value);
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if (Rd < 15)
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{
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@ -359,7 +359,7 @@ int cortex_a8_poll(target_t *target)
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uint8_t saved_apsel = dap_ap_get_select(swjdp);
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dap_ap_select(swjdp, swjdp_debugap);
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retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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{
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dap_ap_select(swjdp, saved_apsel);
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@ -430,21 +430,21 @@ int cortex_a8_halt(target_t *target)
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* and then wait for the core to be halted.
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*/
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retval = mem_ap_write_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
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armv7a->debug_base + CPUDBG_DRCR, 0x1);
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/*
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* enter halting debug mode
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*/
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mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
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retval = mem_ap_write_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
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armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
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if (retval != ERROR_OK)
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goto out;
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do {
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mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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} while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
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target->debug_reason = DBG_REASON_DBGRQ;
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@ -545,11 +545,11 @@ int cortex_a8_resume(struct target_s *target, int current,
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#endif
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/* Restart core and wait for it to be started */
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mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
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mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
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do {
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mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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} while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
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target->debug_reason = DBG_REASON_NOTHALTED;
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@ -596,10 +596,10 @@ int cortex_a8_debug_entry(target_t *target)
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/* Enable the ITR execution once we are in debug mode */
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mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
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armv7a->debug_base + CPUDBG_DSCR, &dscr);
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dscr |= (1 << DSCR_EXT_INT_EN);
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retval = mem_ap_write_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
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armv7a->debug_base + CPUDBG_DSCR, dscr);
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/* Examine debug reason */
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switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
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@ -1029,10 +1029,10 @@ int cortex_a8_set_breakpoint(struct target_s *target,
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brp_list[brp_i].used = 1;
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brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
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brp_list[brp_i].control = control;
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target_write_u32(target, OMAP3530_DEBUG_BASE
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target_write_u32(target, armv7a->debug_base
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+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].value);
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target_write_u32(target, OMAP3530_DEBUG_BASE
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target_write_u32(target, armv7a->debug_base
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+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].control);
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LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
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@ -1095,10 +1095,10 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
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brp_list[brp_i].used = 0;
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brp_list[brp_i].value = 0;
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brp_list[brp_i].control = 0;
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target_write_u32(target, OMAP3530_DEBUG_BASE
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target_write_u32(target, armv7a->debug_base
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+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].control);
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target_write_u32(target, OMAP3530_DEBUG_BASE
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target_write_u32(target, armv7a->debug_base
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+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
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brp_list[brp_i].value);
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}
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@ -1367,34 +1367,37 @@ int cortex_a8_examine(struct target_s *target)
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LOG_DEBUG("TODO");
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/* Here we shall insert a proper ROM Table scan */
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armv7a->debug_base = OMAP3530_DEBUG_BASE;
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/* We do one extra read to ensure DAP is configured,
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* we call ahbap_debugport_init(swjdp) instead
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*/
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ahbap_debugport_init(swjdp);
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mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid);
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mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
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if ((retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
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armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
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{
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LOG_DEBUG("Examine failed");
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return retval;
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}
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if ((retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
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armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
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{
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LOG_DEBUG("Examine failed");
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return retval;
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}
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if ((retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
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armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
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{
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LOG_DEBUG("Examine failed");
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return retval;
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}
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if ((retval = mem_ap_read_atomic_u32(swjdp,
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OMAP3530_DEBUG_BASE + CPUDBG_DIDR, &didr)) != ERROR_OK)
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armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
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{
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LOG_DEBUG("Examine failed");
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return retval;
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