From 450307b66f42f402113c50aefa0fe950ed20cf7d Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Mon, 3 Jul 2017 12:17:07 -0700
Subject: [PATCH] Fix 32-bit build errors.

I only compiled the source. Didn't have the tooling installed to link.
Hopefully that's good enough.
Fixes #71.
---
 src/target/riscv/batch.c     |  4 +++-
 src/target/riscv/riscv-013.c | 11 ++++++-----
 src/target/riscv/riscv.c     |  2 +-
 3 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c
index 5d680d5fa..cb5a10856 100644
--- a/src/target/riscv/batch.c
+++ b/src/target/riscv/batch.c
@@ -94,7 +94,9 @@ size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address)
 	riscv_batch_add_nop(batch);
 
 	batch->read_keys[batch->read_keys_used] = batch->used_scans - 1;
-	LOG_DEBUG("read key %ld for batch 0x%p is %ld (0x%p)", batch->read_keys_used, batch, batch->used_scans - 1, (uint64_t*)batch->data_in + (batch->used_scans + 1));
+	LOG_DEBUG("read key %u for batch 0x%p is %u (0x%p)",
+			(unsigned) batch->read_keys_used, batch, (unsigned) (batch->used_scans - 1),
+			(uint64_t*)batch->data_in + (batch->used_scans + 1));
 	return batch->read_keys_used++;
 }
 
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 60846debe..9d176e948 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1617,9 +1617,10 @@ static int write_memory(struct target *target, target_addr_t address,
 	 * the data was all copied. */
 	riscv_addr_t cur_addr = 0xbadbeef;
 	riscv_addr_t fin_addr = address + (count * size);
-	LOG_DEBUG("writing until final address 0x%016lx", fin_addr);
+	LOG_DEBUG("writing until final address 0x%016" PRIx64, fin_addr);
 	while ((cur_addr = riscv_read_debug_buffer_x(target, d_addr)) < fin_addr) {
-		LOG_DEBUG("transferring burst starting at address 0x%016lx", cur_addr);
+		LOG_DEBUG("transferring burst starting at address 0x%016" PRIx64,
+				cur_addr);
 		riscv_addr_t start = (cur_addr - address) / size;
 		assert (cur_addr > address);
 		struct riscv_batch *batch = riscv_batch_alloc(
@@ -1744,7 +1745,7 @@ static riscv_reg_t riscv013_get_register(struct target *target, int hid, int rid
 		register_read_direct(target, &out, rid);
 	} else if (rid == GDB_REGNO_PC) {
 		register_read_direct(target, &out, GDB_REGNO_DPC);
-		LOG_DEBUG("read PC from DPC: 0x%016lx", out);
+		LOG_DEBUG("read PC from DPC: 0x%016" PRIx64, out);
 	} else if (rid == GDB_REGNO_PRIV) {
 		uint64_t dcsr;
 		register_read_direct(target, &dcsr, CSR_DCSR);
@@ -1772,11 +1773,11 @@ static void riscv013_set_register(struct target *target, int hid, int rid, uint6
 	if (rid <= GDB_REGNO_XPR31) {
 		register_write_direct(target, rid, value);
 	} else if (rid == GDB_REGNO_PC) {
-		LOG_DEBUG("writing PC to DPC: 0x%016lx", value);
+		LOG_DEBUG("writing PC to DPC: 0x%016" PRIx64, value);
 		register_write_direct(target, GDB_REGNO_DPC, value);
 		uint64_t actual_value;
 		register_read_direct(target, &actual_value, GDB_REGNO_DPC);
-		LOG_DEBUG("  actual DPC written: 0x%016lx", actual_value);
+		LOG_DEBUG("  actual DPC written: 0x%016" PRIx64, actual_value);
 		assert(value == actual_value);
 	} else if (rid == GDB_REGNO_PRIV) {
 		uint64_t dcsr;
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 7a40467f1..83e73eff3 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1030,7 +1030,7 @@ void riscv_set_current_hartid(struct target *target, int hartid)
 	/* Avoid invalidating the register cache all the time. */
 	if (r->registers_initialized
 			&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
-			&& target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (long)riscv_xlen(target)
+			&& target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (unsigned)riscv_xlen(target)
 			&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
 		LOG_DEBUG("registers already initialized, skipping");
 		return;