flash/nor: Add Infineon XMC1000 flash driver
The XMC1000 family uses a very different flash interface from XMC4000. Tested on XMC 2Go and XMC1100 Boot Kit. Change-Id: I3edaed420ef1c0fb89fdf221022c8b04163d41b3 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3418 Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Tested-by: jenkins__archive__
Andreas Färber
Freddie Chopin
parent
edf2cdc80b
commit
44d2c7b416
2
README
2
README
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@ -130,7 +130,7 @@ ADUC702x, AT91SAM, AVR, CFI, DSP5680xx, EFM32, EM357, FM3, FM4, Kinetis,
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LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPCSPIFI, Marvell QSPI,
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LPC8xx/LPC1xxx/LPC2xxx/LPC541xx, LPC2900, LPCSPIFI, Marvell QSPI,
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Milandr, NIIET, NuMicro, PIC32mx, PSoC4, SiM3x, Stellaris, STM32, STMSMI,
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Milandr, NIIET, NuMicro, PIC32mx, PSoC4, SiM3x, Stellaris, STM32, STMSMI,
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STR7x, STR9x, nRF51; NAND controllers of AT91SAM9, LPC3180, LPC32xx,
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STR7x, STR9x, nRF51; NAND controllers of AT91SAM9, LPC3180, LPC32xx,
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i.MX31, MXC, NUC910, Orion/Kirkwood, S3C24xx, S3C6400, XMC4xxx.
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i.MX31, MXC, NUC910, Orion/Kirkwood, S3C24xx, S3C6400, XMC1xxx, XMC4xxx.
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==================
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==================
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@ -0,0 +1,30 @@
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BIN2C = ../../../../src/helper/bin2char.sh
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CROSS_COMPILE ?= arm-none-eabi-
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CC=$(CROSS_COMPILE)gcc
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OBJCOPY=$(CROSS_COMPILE)objcopy
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OBJDUMP=$(CROSS_COMPILE)objdump
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all: erase.inc erase_check.inc write.inc
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.PHONY: clean
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.INTERMEDIATE: erase.elf erase_check.elf write.elf
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erase.elf erase_check.elf write.elf: xmc1xxx.S
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%.elf: %.S
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$(CC) -static -nostartfiles $< -o $@
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%.lst: %.elf
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$(OBJDUMP) -S $< > $@
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%.bin: %.elf
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$(OBJCOPY) -Obinary $< $@
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%.inc: %.bin
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$(BIN2C) < $< > $@
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clean:
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-rm -f *.elf *.lst *.bin *.inc
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@ -0,0 +1,53 @@
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/*
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* Infineon XMC1000 flash sectors erase
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*
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* Copyright (c) 2016 Andreas Färber
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*
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* Based on XMC1100 AA-Step Reference Manual
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*
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* License: GPL-2.0+
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*/
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#include "xmc1xxx.S"
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#define DUMMY_VALUE 0x42
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.macro erase_page, nvmbase, addr, tmp, tmp2
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movs \tmp, #DUMMY_VALUE
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str \tmp, [\addr]
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busy_wait \nvmbase, \tmp, \tmp2
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.endm
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.macro erase, nvmbase, addr, end, tmp, tmp2
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movs \tmp, #NVMPROG_ACTION_PAGE_ERASE_CONTINUOUS
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strh \tmp, [\nvmbase, #NVMPROG]
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2001:
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erase_page \nvmbase, \addr, \tmp, \tmp2
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movs \tmp, #(NVM_PAGE_SIZE - 1)
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adds \tmp, \tmp, #1
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add \addr, \addr, \tmp
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cmp \addr, \end
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blt 2001b
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movs \tmp, #NVMPROG_ACTION_IDLE
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strh \tmp, [\nvmbase, #NVMPROG]
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.endm
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/*
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* r0 = 0x40050000
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* r1 = e.g. 0x10001000
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* r2 = e.g. 0x10011000
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* NVMPROG.ACTION = 0x00
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*/
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erase:
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erase r0, r1, r2, r3, r4
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bkpt #0
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@ -0,0 +1,4 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0xa2,0x23,0x83,0x80,0x42,0x23,0x0b,0x60,0x03,0x88,0x01,0x24,0x23,0x40,0xa3,0x42,
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0xfa,0xd0,0xff,0x23,0x01,0x33,0x19,0x44,0x91,0x42,0xf3,0xdb,0x00,0x23,0x83,0x80,
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0x00,0xbe,
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@ -0,0 +1,67 @@
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/*
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* Infineon XMC1000 flash sector erase check
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*
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* Copyright (c) 2016 Andreas Färber
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*
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* Based on XMC1100 AA-Step Reference Manual
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*
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* License: GPL-2.0+
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*/
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#include "xmc1xxx.S"
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.macro verify_block, nvmbase, addr, tmp, tmp2
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movs \tmp, #0x00
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mvns \tmp, \tmp
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str \tmp, [\addr, #0x0]
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str \tmp, [\addr, #0x4]
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str \tmp, [\addr, #0x8]
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str \tmp, [\addr, #0xC]
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busy_wait \nvmbase, \tmp, \tmp2
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.endm
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.macro erase_check, nvmbase, addr, end, tmp, tmp2
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ldrh \tmp, [\nvmbase, #NVMCONF]
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movs \tmp2, #NVMCONF_HRLEV_MASK
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mvns \tmp2, \tmp2
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ands \tmp, \tmp, \tmp2
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movs \tmp2, #NVMCONF_HRLEV_HRE
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orrs \tmp, \tmp, \tmp2
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strh \tmp, [\nvmbase, #NVMCONF]
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movs \tmp, #NVMPROG_ACTION_VERIFY_CONTINUOUS
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strh \tmp, [\nvmbase, #NVMPROG]
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2001:
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verify_block \nvmbase, \addr, \tmp, \tmp2
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ldrh \tmp, [\nvmbase, #NVMSTATUS]
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movs \tmp2, #NVMSTATUS_VERR_MASK
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ands \tmp, \tmp, \tmp2
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cmp \tmp, #NVMSTATUS_VERR_NOFAIL
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bne 2010f
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adds \addr, \addr, #NVM_BLOCK_SIZE
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cmp \addr, \end
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blt 2001b
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2010:
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movs \tmp, #NVMPROG_ACTION_IDLE
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strh \tmp, [\nvmbase, #NVMPROG]
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.endm
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/*
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* r0 = 0x40050000
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* r1 = e.g. 0x10001000
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* r2 = e.g. 0x10002000
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* NVMPROG.ACTION = 0x00
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*/
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erase_check:
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erase_check r0, r1, r2, r3, r4
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bkpt #0
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@ -0,0 +1,5 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x03,0x89,0x06,0x24,0xe4,0x43,0x23,0x40,0x04,0x24,0x23,0x43,0x03,0x81,0xe0,0x23,
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0x83,0x80,0x00,0x23,0xdb,0x43,0x0b,0x60,0x4b,0x60,0x8b,0x60,0xcb,0x60,0x03,0x88,
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0x01,0x24,0x23,0x40,0xa3,0x42,0xfa,0xd0,0x03,0x88,0x0c,0x24,0x23,0x40,0x00,0x2b,
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0x02,0xd1,0x10,0x31,0x91,0x42,0xec,0xdb,0x00,0x23,0x83,0x80,0x00,0xbe,
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@ -0,0 +1,58 @@
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/*
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* Infineon XMC1000 flash write
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*
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* Copyright (c) 2016 Andreas Färber
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*
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* Based on XMC1100 AA-Step Reference Manual
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*
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* License: GPL-2.0+
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*/
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#include "xmc1xxx.S"
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.macro write_block, nvmbase, dest, src, tmp, tmp2
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ldr \tmp, [\src, #0x0]
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str \tmp, [\dest, #0x0]
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ldr \tmp, [\src, #0x4]
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str \tmp, [\dest, #0x4]
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ldr \tmp, [\src, #0x8]
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str \tmp, [\dest, #0x8]
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ldr \tmp, [\src, #0xc]
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str \tmp, [\dest, #0xc]
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busy_wait \nvmbase, \tmp, \tmp2
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.endm
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.macro write, nvmbase, dest, src, count, tmp, tmp2
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movs \tmp, #NVMPROG_ACTION_WRITE_CONTINUOUS
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strh \tmp, [\nvmbase, #NVMPROG]
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1001:
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write_block \nvmbase, \dest, \src, \tmp, \tmp2
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adds \dest, \dest, #NVM_BLOCK_SIZE
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adds \src, \src, #NVM_BLOCK_SIZE
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subs \count, \count, #1
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cmp \count, #0
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bgt 1001b
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movs \tmp, #NVMPROG_ACTION_IDLE
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strh \tmp, [\nvmbase, #NVMPROG]
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.endm
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/*
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* r0 = 0x40050000
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* r1 = e.g. 0x10001000
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* r2 = e.g. 0x20000000
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* r3 = e.g. 1
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* NVMPROG.ACTION = 0x00
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*/
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write:
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write r0, r1, r2, r3, r4, r5
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bkpt #0
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@ -0,0 +1,4 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0xa1,0x24,0x84,0x80,0x14,0x68,0x0c,0x60,0x54,0x68,0x4c,0x60,0x94,0x68,0x8c,0x60,
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0xd4,0x68,0xcc,0x60,0x04,0x88,0x01,0x25,0x2c,0x40,0xac,0x42,0xfa,0xd0,0x10,0x31,
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0x10,0x32,0x01,0x3b,0x00,0x2b,0xed,0xdc,0x00,0x24,0x84,0x80,0x00,0xbe,
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@ -0,0 +1,46 @@
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/*
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* Infineon XMC1000 flash
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*
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* Copyright (c) 2016 Andreas Färber
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*
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* Based on XMC1100 AA-Step Reference Manual
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*
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* License: GPL-2.0+
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*/
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.text
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.syntax unified
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.cpu cortex-m0
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.thumb
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.thumb_func
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#define NVMSTATUS 0x00
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#define NVMPROG 0x04
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#define NVMCONF 0x08
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#define NVMSTATUS_BUSY (1 << 0)
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#define NVMSTATUS_VERR_NOFAIL (0x0 << 2)
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#define NVMSTATUS_VERR_MASK (0x3 << 2)
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#define NVMPROG_ACTION_IDLE 0x00
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#define NVMPROG_ACTION_WRITE_CONTINUOUS 0xA1
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#define NVMPROG_ACTION_PAGE_ERASE_CONTINUOUS 0xA2
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#define NVMPROG_ACTION_VERIFY_CONTINUOUS 0xE0
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#define NVMCONF_HRLEV_NR (0x0 << 1)
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#define NVMCONF_HRLEV_HRE (0x2 << 1)
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#define NVMCONF_HRLEV_MASK (0x3 << 1)
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#define NVM_WORD_SIZE 4
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#define NVM_BLOCK_SIZE (4 * NVM_WORD_SIZE)
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#define NVM_PAGE_SIZE (16 * NVM_BLOCK_SIZE)
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.macro busy_wait, nvmbase, tmp, tmp2
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1:
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ldrh \tmp, [\nvmbase, #NVMSTATUS]
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movs \tmp2, #NVMSTATUS_BUSY
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ands \tmp, \tmp, \tmp2
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cmp \tmp, \tmp2
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beq 1b
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.endm
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@ -5977,6 +5977,11 @@ the flash clock.
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@end deffn
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@end deffn
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@end deffn
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@end deffn
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@deffn {Flash Driver} xmc1xxx
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All members of the XMC1xxx microcontroller family from Infineon.
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This driver does not require the chip and bus width to be specified.
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@end deffn
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@deffn {Flash Driver} xmc4xxx
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@deffn {Flash Driver} xmc4xxx
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All members of the XMC4xxx microcontroller family from Infineon.
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All members of the XMC4xxx microcontroller family from Infineon.
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This driver does not require the chip and bus width to be specified.
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This driver does not require the chip and bus width to be specified.
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@ -53,6 +53,7 @@ NOR_DRIVERS = \
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str9xpec.c \
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str9xpec.c \
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tms470.c \
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tms470.c \
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virtual.c \
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virtual.c \
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xmc1xxx.c \
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xmc4xxx.c
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xmc4xxx.c
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noinst_HEADERS = \
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noinst_HEADERS = \
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@ -65,6 +65,7 @@ extern struct flash_driver str9x_flash;
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extern struct flash_driver str9xpec_flash;
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extern struct flash_driver str9xpec_flash;
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extern struct flash_driver tms470_flash;
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extern struct flash_driver tms470_flash;
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extern struct flash_driver virtual_flash;
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extern struct flash_driver virtual_flash;
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extern struct flash_driver xmc1xxx_flash;
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extern struct flash_driver xmc4xxx_flash;
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extern struct flash_driver xmc4xxx_flash;
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/**
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/**
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@ -115,6 +116,7 @@ static struct flash_driver *flash_drivers[] = {
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&str9xpec_flash,
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&str9xpec_flash,
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&tms470_flash,
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&tms470_flash,
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&virtual_flash,
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&virtual_flash,
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&xmc1xxx_flash,
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&xmc4xxx_flash,
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&xmc4xxx_flash,
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NULL,
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NULL,
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};
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};
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/*
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* XMC1000 flash driver
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*
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* Copyright (c) 2016 Andreas Färber
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*
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* License: GPL-2.0+
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "imp.h"
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#include <helper/binarybuffer.h>
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#include <target/algorithm.h>
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#include <target/armv7m.h>
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#define FLASH_BASE 0x10000000
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#define PAU_BASE 0x40000000
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#define SCU_BASE 0x40010000
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#define NVM_BASE 0x40050000
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#define FLASH_CS0 (FLASH_BASE + 0xf00)
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||||||
|
#define PAU_FLSIZE (PAU_BASE + 0x404)
|
||||||
|
|
||||||
|
#define SCU_IDCHIP (SCU_BASE + 0x004)
|
||||||
|
|
||||||
|
#define NVMSTATUS (NVM_BASE + 0x00)
|
||||||
|
#define NVMPROG (NVM_BASE + 0x04)
|
||||||
|
#define NVMCONF (NVM_BASE + 0x08)
|
||||||
|
|
||||||
|
#define NVMSTATUS_BUSY (1 << 0)
|
||||||
|
#define NVMSTATUS_VERR_MASK (0x3 << 2)
|
||||||
|
|
||||||
|
#define NVMPROG_ACTION_OPTYPE_IDLE_VERIFY (0 << 0)
|
||||||
|
#define NVMPROG_ACTION_OPTYPE_WRITE (1 << 0)
|
||||||
|
#define NVMPROG_ACTION_OPTYPE_PAGE_ERASE (2 << 0)
|
||||||
|
|
||||||
|
#define NVMPROG_ACTION_ONE_SHOT_ONCE (1 << 4)
|
||||||
|
#define NVMPROG_ACTION_ONE_SHOT_CONTINUOUS (2 << 4)
|
||||||
|
|
||||||
|
#define NVMPROG_ACTION_VERIFY_EACH (1 << 6)
|
||||||
|
#define NVMPROG_ACTION_VERIFY_NO (2 << 6)
|
||||||
|
#define NVMPROG_ACTION_VERIFY_ARRAY (3 << 6)
|
||||||
|
|
||||||
|
#define NVMPROG_ACTION_IDLE 0x00
|
||||||
|
#define NVMPROG_ACTION_MASK 0xff
|
||||||
|
|
||||||
|
#define NVM_WORD_SIZE 4
|
||||||
|
#define NVM_BLOCK_SIZE (4 * NVM_WORD_SIZE)
|
||||||
|
#define NVM_PAGE_SIZE (16 * NVM_BLOCK_SIZE)
|
||||||
|
|
||||||
|
struct xmc1xxx_flash_bank {
|
||||||
|
bool probed;
|
||||||
|
};
|
||||||
|
|
||||||
|
static int xmc1xxx_nvm_set_idle(struct target *target)
|
||||||
|
{
|
||||||
|
return target_write_u16(target, NVMPROG, NVMPROG_ACTION_IDLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_nvm_check_idle(struct target *target)
|
||||||
|
{
|
||||||
|
uint16_t val;
|
||||||
|
int retval;
|
||||||
|
|
||||||
|
retval = target_read_u16(target, NVMPROG, &val);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
return retval;
|
||||||
|
if ((val & NVMPROG_ACTION_MASK) != NVMPROG_ACTION_IDLE) {
|
||||||
|
LOG_WARNING("NVMPROG.ACTION");
|
||||||
|
retval = xmc1xxx_nvm_set_idle(target);
|
||||||
|
}
|
||||||
|
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_erase(struct flash_bank *bank, int first, int last)
|
||||||
|
{
|
||||||
|
struct target *target = bank->target;
|
||||||
|
struct working_area *workarea;
|
||||||
|
struct reg_param reg_params[3];
|
||||||
|
struct armv7m_algorithm armv7m_algo;
|
||||||
|
unsigned i;
|
||||||
|
int retval, sector;
|
||||||
|
const uint8_t erase_code[] = {
|
||||||
|
#include "../../../contrib/loaders/flash/xmc1xxx/erase.inc"
|
||||||
|
};
|
||||||
|
|
||||||
|
LOG_DEBUG("Infineon XMC1000 erase sectors %d to %d", first, last);
|
||||||
|
|
||||||
|
if (bank->target->state != TARGET_HALTED) {
|
||||||
|
LOG_WARNING("Cannot communicate... target not halted.");
|
||||||
|
return ERROR_TARGET_NOT_HALTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
retval = xmc1xxx_nvm_check_idle(target);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
return retval;
|
||||||
|
|
||||||
|
retval = target_alloc_working_area(target, sizeof(erase_code),
|
||||||
|
&workarea);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("No working area available.");
|
||||||
|
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||||
|
goto err_alloc_code;
|
||||||
|
}
|
||||||
|
retval = target_write_buffer(target, workarea->address,
|
||||||
|
sizeof(erase_code), erase_code);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
goto err_write_code;
|
||||||
|
|
||||||
|
armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
|
||||||
|
armv7m_algo.core_mode = ARM_MODE_THREAD;
|
||||||
|
|
||||||
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
||||||
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
||||||
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
||||||
|
|
||||||
|
buf_set_u32(reg_params[0].value, 0, 32, NVM_BASE);
|
||||||
|
buf_set_u32(reg_params[1].value, 0, 32, bank->base +
|
||||||
|
bank->sectors[first].offset);
|
||||||
|
buf_set_u32(reg_params[2].value, 0, 32, bank->base +
|
||||||
|
bank->sectors[last].offset + bank->sectors[last].size);
|
||||||
|
|
||||||
|
retval = target_run_algorithm(target,
|
||||||
|
0, NULL,
|
||||||
|
ARRAY_SIZE(reg_params), reg_params,
|
||||||
|
workarea->address, 0,
|
||||||
|
1000, &armv7m_algo);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Error executing flash sector erase "
|
||||||
|
"programming algorithm");
|
||||||
|
retval = xmc1xxx_nvm_set_idle(target);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
LOG_WARNING("Couldn't restore NVMPROG.ACTION");
|
||||||
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
||||||
|
goto err_run;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (sector = first; sector <= last; sector++)
|
||||||
|
bank->sectors[sector].is_erased = 1;
|
||||||
|
|
||||||
|
err_run:
|
||||||
|
for (i = 0; i < ARRAY_SIZE(reg_params); i++)
|
||||||
|
destroy_reg_param(®_params[i]);
|
||||||
|
|
||||||
|
err_write_code:
|
||||||
|
target_free_working_area(target, workarea);
|
||||||
|
|
||||||
|
err_alloc_code:
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_erase_check(struct flash_bank *bank)
|
||||||
|
{
|
||||||
|
struct target *target = bank->target;
|
||||||
|
struct working_area *workarea;
|
||||||
|
struct reg_param reg_params[3];
|
||||||
|
struct armv7m_algorithm armv7m_algo;
|
||||||
|
uint16_t val;
|
||||||
|
unsigned i;
|
||||||
|
int retval, sector;
|
||||||
|
const uint8_t erase_check_code[] = {
|
||||||
|
#include "../../../contrib/loaders/flash/xmc1xxx/erase_check.inc"
|
||||||
|
};
|
||||||
|
|
||||||
|
if (bank->target->state != TARGET_HALTED) {
|
||||||
|
LOG_WARNING("Cannot communicate... target not halted.");
|
||||||
|
return ERROR_TARGET_NOT_HALTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
retval = target_alloc_working_area(target, sizeof(erase_check_code),
|
||||||
|
&workarea);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("No working area available.");
|
||||||
|
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||||
|
goto err_alloc_code;
|
||||||
|
}
|
||||||
|
retval = target_write_buffer(target, workarea->address,
|
||||||
|
sizeof(erase_check_code), erase_check_code);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
goto err_write_code;
|
||||||
|
|
||||||
|
armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
|
||||||
|
armv7m_algo.core_mode = ARM_MODE_THREAD;
|
||||||
|
|
||||||
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
||||||
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
||||||
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
||||||
|
|
||||||
|
buf_set_u32(reg_params[0].value, 0, 32, NVM_BASE);
|
||||||
|
|
||||||
|
for (sector = 0; sector < bank->num_sectors; sector++) {
|
||||||
|
uint32_t start = bank->base + bank->sectors[sector].offset;
|
||||||
|
buf_set_u32(reg_params[1].value, 0, 32, start);
|
||||||
|
buf_set_u32(reg_params[2].value, 0, 32, start + bank->sectors[sector].size);
|
||||||
|
|
||||||
|
retval = xmc1xxx_nvm_check_idle(target);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
goto err_nvmprog;
|
||||||
|
|
||||||
|
LOG_DEBUG("Erase-checking 0x%08" PRIx32, start);
|
||||||
|
retval = target_run_algorithm(target,
|
||||||
|
0, NULL,
|
||||||
|
ARRAY_SIZE(reg_params), reg_params,
|
||||||
|
workarea->address, 0,
|
||||||
|
1000, &armv7m_algo);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Error executing flash sector erase check "
|
||||||
|
"programming algorithm");
|
||||||
|
retval = xmc1xxx_nvm_set_idle(target);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
LOG_WARNING("Couldn't restore NVMPROG.ACTION");
|
||||||
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
||||||
|
goto err_run;
|
||||||
|
}
|
||||||
|
|
||||||
|
retval = target_read_u16(target, NVMSTATUS, &val);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Couldn't read NVMSTATUS");
|
||||||
|
goto err_nvmstatus;
|
||||||
|
}
|
||||||
|
bank->sectors[sector].is_erased = (val & NVMSTATUS_VERR_MASK) ? 0 : 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
err_nvmstatus:
|
||||||
|
err_run:
|
||||||
|
err_nvmprog:
|
||||||
|
for (i = 0; i < ARRAY_SIZE(reg_params); i++)
|
||||||
|
destroy_reg_param(®_params[i]);
|
||||||
|
|
||||||
|
err_write_code:
|
||||||
|
target_free_working_area(target, workarea);
|
||||||
|
|
||||||
|
err_alloc_code:
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_write(struct flash_bank *bank, const uint8_t *buffer,
|
||||||
|
uint32_t offset, uint32_t byte_count)
|
||||||
|
{
|
||||||
|
struct target *target = bank->target;
|
||||||
|
struct working_area *code_workarea, *data_workarea;
|
||||||
|
struct reg_param reg_params[4];
|
||||||
|
struct armv7m_algorithm armv7m_algo;
|
||||||
|
uint32_t block_count = DIV_ROUND_UP(byte_count, NVM_BLOCK_SIZE);
|
||||||
|
unsigned i;
|
||||||
|
int retval;
|
||||||
|
const uint8_t write_code[] = {
|
||||||
|
#include "../../../contrib/loaders/flash/xmc1xxx/write.inc"
|
||||||
|
};
|
||||||
|
|
||||||
|
LOG_DEBUG("Infineon XMC1000 write at 0x%08" PRIx32 " (%" PRId32 " bytes)",
|
||||||
|
offset, byte_count);
|
||||||
|
|
||||||
|
if (offset & (NVM_BLOCK_SIZE - 1)) {
|
||||||
|
LOG_ERROR("offset 0x%" PRIx32 " breaks required block alignment",
|
||||||
|
offset);
|
||||||
|
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
|
||||||
|
}
|
||||||
|
if (byte_count & (NVM_BLOCK_SIZE - 1)) {
|
||||||
|
LOG_WARNING("length %" PRId32 " is not block aligned, rounding up",
|
||||||
|
byte_count);
|
||||||
|
}
|
||||||
|
|
||||||
|
if (target->state != TARGET_HALTED) {
|
||||||
|
LOG_WARNING("Cannot communicate... target not halted.");
|
||||||
|
return ERROR_TARGET_NOT_HALTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
retval = target_alloc_working_area(target, sizeof(write_code),
|
||||||
|
&code_workarea);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("No working area available for write code.");
|
||||||
|
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||||
|
goto err_alloc_code;
|
||||||
|
}
|
||||||
|
retval = target_write_buffer(target, code_workarea->address,
|
||||||
|
sizeof(write_code), write_code);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
goto err_write_code;
|
||||||
|
|
||||||
|
retval = target_alloc_working_area(target, MAX(NVM_BLOCK_SIZE,
|
||||||
|
MIN(block_count * NVM_BLOCK_SIZE, target_get_working_area_avail(target))),
|
||||||
|
&data_workarea);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("No working area available for write data.");
|
||||||
|
retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
|
||||||
|
goto err_alloc_data;
|
||||||
|
}
|
||||||
|
|
||||||
|
armv7m_algo.common_magic = ARMV7M_COMMON_MAGIC;
|
||||||
|
armv7m_algo.core_mode = ARM_MODE_THREAD;
|
||||||
|
|
||||||
|
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
|
||||||
|
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
|
||||||
|
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
|
||||||
|
init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
|
||||||
|
|
||||||
|
buf_set_u32(reg_params[0].value, 0, 32, NVM_BASE);
|
||||||
|
|
||||||
|
while (byte_count > 0) {
|
||||||
|
uint32_t blocks = MIN(block_count, data_workarea->size / NVM_BLOCK_SIZE);
|
||||||
|
uint32_t addr = bank->base + offset;
|
||||||
|
|
||||||
|
LOG_DEBUG("copying %" PRId32 " bytes to SRAM 0x%08" PRIx32,
|
||||||
|
MIN(blocks * NVM_BLOCK_SIZE, byte_count),
|
||||||
|
data_workarea->address);
|
||||||
|
|
||||||
|
retval = target_write_buffer(target, data_workarea->address,
|
||||||
|
MIN(blocks * NVM_BLOCK_SIZE, byte_count), buffer);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Error writing data buffer");
|
||||||
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
||||||
|
goto err_write_data;
|
||||||
|
}
|
||||||
|
if (byte_count < blocks * NVM_BLOCK_SIZE) {
|
||||||
|
retval = target_write_memory(target,
|
||||||
|
data_workarea->address + byte_count, 1,
|
||||||
|
blocks * NVM_BLOCK_SIZE - byte_count,
|
||||||
|
&bank->default_padded_value);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Error writing data padding");
|
||||||
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
||||||
|
goto err_write_pad;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_DEBUG("writing 0x%08" PRIx32 "-0x%08" PRIx32 " (%" PRId32 "x)",
|
||||||
|
addr, addr + blocks * NVM_BLOCK_SIZE - 1, blocks);
|
||||||
|
|
||||||
|
retval = xmc1xxx_nvm_check_idle(target);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
goto err_nvmprog;
|
||||||
|
|
||||||
|
buf_set_u32(reg_params[1].value, 0, 32, addr);
|
||||||
|
buf_set_u32(reg_params[2].value, 0, 32, data_workarea->address);
|
||||||
|
buf_set_u32(reg_params[3].value, 0, 32, blocks);
|
||||||
|
|
||||||
|
retval = target_run_algorithm(target,
|
||||||
|
0, NULL,
|
||||||
|
ARRAY_SIZE(reg_params), reg_params,
|
||||||
|
code_workarea->address, 0,
|
||||||
|
5 * 60 * 1000, &armv7m_algo);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Error executing flash write "
|
||||||
|
"programming algorithm");
|
||||||
|
retval = xmc1xxx_nvm_set_idle(target);
|
||||||
|
if (retval != ERROR_OK)
|
||||||
|
LOG_WARNING("Couldn't restore NVMPROG.ACTION");
|
||||||
|
retval = ERROR_FLASH_OPERATION_FAILED;
|
||||||
|
goto err_run;
|
||||||
|
}
|
||||||
|
|
||||||
|
block_count -= blocks;
|
||||||
|
offset += blocks * NVM_BLOCK_SIZE;
|
||||||
|
buffer += blocks * NVM_BLOCK_SIZE;
|
||||||
|
byte_count -= MIN(blocks * NVM_BLOCK_SIZE, byte_count);
|
||||||
|
}
|
||||||
|
|
||||||
|
err_run:
|
||||||
|
err_nvmprog:
|
||||||
|
err_write_pad:
|
||||||
|
err_write_data:
|
||||||
|
for (i = 0; i < ARRAY_SIZE(reg_params); i++)
|
||||||
|
destroy_reg_param(®_params[i]);
|
||||||
|
|
||||||
|
target_free_working_area(target, data_workarea);
|
||||||
|
err_alloc_data:
|
||||||
|
err_write_code:
|
||||||
|
target_free_working_area(target, code_workarea);
|
||||||
|
|
||||||
|
err_alloc_code:
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_protect_check(struct flash_bank *bank)
|
||||||
|
{
|
||||||
|
uint32_t nvmconf;
|
||||||
|
int i, num_protected, retval;
|
||||||
|
|
||||||
|
if (bank->target->state != TARGET_HALTED) {
|
||||||
|
LOG_WARNING("Cannot communicate... target not halted.");
|
||||||
|
return ERROR_TARGET_NOT_HALTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
retval = target_read_u32(bank->target, NVMCONF, &nvmconf);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Cannot read NVMCONF register.");
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
LOG_DEBUG("NVMCONF = %08" PRIx32, nvmconf);
|
||||||
|
|
||||||
|
num_protected = (nvmconf >> 4) & 0xff;
|
||||||
|
|
||||||
|
for (i = 0; i < bank->num_sectors; i++)
|
||||||
|
bank->sectors[i].is_protected = (i < num_protected) ? 1 : 0;
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_size)
|
||||||
|
{
|
||||||
|
uint32_t chipid[8];
|
||||||
|
int i, retval;
|
||||||
|
|
||||||
|
if (bank->target->state != TARGET_HALTED) {
|
||||||
|
LOG_WARNING("Cannot communicate... target not halted.");
|
||||||
|
return ERROR_TARGET_NOT_HALTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Obtain the 8-word Chip Identification Number */
|
||||||
|
for (i = 0; i < 7; i++) {
|
||||||
|
retval = target_read_u32(bank->target, FLASH_CS0 + i * 4, &chipid[i]);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Cannot read CS0 register %i.", i);
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
LOG_DEBUG("ID[%d] = %08" PRIX32, i, chipid[i]);
|
||||||
|
}
|
||||||
|
retval = target_read_u32(bank->target, SCU_BASE + 0x000, &chipid[7]);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Cannot read DBGROMID register.");
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
LOG_DEBUG("ID[7] = %08" PRIX32, chipid[7]);
|
||||||
|
|
||||||
|
snprintf(buf, buf_size, "XMC%" PRIx32 "00 %X flash %uKB ROM %uKB SRAM %uKB",
|
||||||
|
(chipid[0] >> 12) & 0xff,
|
||||||
|
0xAA + (chipid[7] >> 28) - 1,
|
||||||
|
(((chipid[6] >> 12) & 0x3f) - 1) * 4,
|
||||||
|
(((chipid[4] >> 8) & 0x3f) * 256) / 1024,
|
||||||
|
(((chipid[5] >> 8) & 0x1f) * 256 * 4) / 1024);
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_probe(struct flash_bank *bank)
|
||||||
|
{
|
||||||
|
struct xmc1xxx_flash_bank *xmc_bank = bank->driver_priv;
|
||||||
|
uint32_t flash_addr = bank->base;
|
||||||
|
uint32_t idchip, flsize;
|
||||||
|
int i, retval;
|
||||||
|
|
||||||
|
if (xmc_bank->probed)
|
||||||
|
return ERROR_OK;
|
||||||
|
|
||||||
|
if (bank->target->state != TARGET_HALTED) {
|
||||||
|
LOG_WARNING("Cannot communicate... target not halted.");
|
||||||
|
return ERROR_TARGET_NOT_HALTED;
|
||||||
|
}
|
||||||
|
|
||||||
|
retval = target_read_u32(bank->target, SCU_IDCHIP, &idchip);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Cannot read IDCHIP register.");
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((idchip & 0xffff0000) != 0x10000) {
|
||||||
|
LOG_ERROR("IDCHIP register does not match XMC1xxx.");
|
||||||
|
return ERROR_FAIL;
|
||||||
|
}
|
||||||
|
|
||||||
|
LOG_DEBUG("IDCHIP = %08" PRIx32, idchip);
|
||||||
|
|
||||||
|
retval = target_read_u32(bank->target, PAU_FLSIZE, &flsize);
|
||||||
|
if (retval != ERROR_OK) {
|
||||||
|
LOG_ERROR("Cannot read FLSIZE register.");
|
||||||
|
return retval;
|
||||||
|
}
|
||||||
|
|
||||||
|
bank->num_sectors = 1 + ((flsize >> 12) & 0x3f) - 1;
|
||||||
|
bank->size = bank->num_sectors * 4 * 1024;
|
||||||
|
bank->sectors = calloc(bank->num_sectors,
|
||||||
|
sizeof(struct flash_sector));
|
||||||
|
for (i = 0; i < bank->num_sectors; i++) {
|
||||||
|
if (i == 0) {
|
||||||
|
bank->sectors[i].size = 0x200;
|
||||||
|
bank->sectors[i].offset = 0xE00;
|
||||||
|
flash_addr += 0x1000;
|
||||||
|
} else {
|
||||||
|
bank->sectors[i].size = 4 * 1024;
|
||||||
|
bank->sectors[i].offset = flash_addr - bank->base;
|
||||||
|
flash_addr += bank->sectors[i].size;
|
||||||
|
}
|
||||||
|
bank->sectors[i].is_erased = -1;
|
||||||
|
bank->sectors[i].is_protected = -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
xmc_bank->probed = true;
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int xmc1xxx_auto_probe(struct flash_bank *bank)
|
||||||
|
{
|
||||||
|
struct xmc1xxx_flash_bank *xmc_bank = bank->driver_priv;
|
||||||
|
|
||||||
|
if (xmc_bank->probed)
|
||||||
|
return ERROR_OK;
|
||||||
|
|
||||||
|
return xmc1xxx_probe(bank);
|
||||||
|
}
|
||||||
|
|
||||||
|
FLASH_BANK_COMMAND_HANDLER(xmc1xxx_flash_bank_command)
|
||||||
|
{
|
||||||
|
struct xmc1xxx_flash_bank *xmc_bank;
|
||||||
|
|
||||||
|
xmc_bank = malloc(sizeof(struct xmc1xxx_flash_bank));
|
||||||
|
if (!xmc_bank)
|
||||||
|
return ERROR_FLASH_OPERATION_FAILED;
|
||||||
|
|
||||||
|
xmc_bank->probed = false;
|
||||||
|
|
||||||
|
bank->driver_priv = xmc_bank;
|
||||||
|
|
||||||
|
return ERROR_OK;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const struct command_registration xmc1xxx_exec_command_handlers[] = {
|
||||||
|
COMMAND_REGISTRATION_DONE
|
||||||
|
};
|
||||||
|
|
||||||
|
static const struct command_registration xmc1xxx_command_handlers[] = {
|
||||||
|
{
|
||||||
|
.name = "xmc1xxx",
|
||||||
|
.mode = COMMAND_ANY,
|
||||||
|
.help = "xmc1xxx flash command group",
|
||||||
|
.usage = "",
|
||||||
|
.chain = xmc1xxx_exec_command_handlers,
|
||||||
|
},
|
||||||
|
COMMAND_REGISTRATION_DONE
|
||||||
|
};
|
||||||
|
|
||||||
|
struct flash_driver xmc1xxx_flash = {
|
||||||
|
.name = "xmc1xxx",
|
||||||
|
.commands = xmc1xxx_command_handlers,
|
||||||
|
.flash_bank_command = xmc1xxx_flash_bank_command,
|
||||||
|
.info = xmc1xxx_get_info_command,
|
||||||
|
.probe = xmc1xxx_probe,
|
||||||
|
.auto_probe = xmc1xxx_auto_probe,
|
||||||
|
.protect_check = xmc1xxx_protect_check,
|
||||||
|
.read = default_flash_read,
|
||||||
|
.erase = xmc1xxx_erase,
|
||||||
|
.erase_check = xmc1xxx_erase_check,
|
||||||
|
.write = xmc1xxx_write,
|
||||||
|
};
|
||||||
|
|
@ -9,6 +9,7 @@ source [find interface/jlink.cfg]
|
||||||
transport select swd
|
transport select swd
|
||||||
|
|
||||||
set CHIPNAME xmc1100
|
set CHIPNAME xmc1100
|
||||||
|
set WORKAREASIZE 0x4000
|
||||||
source [find target/xmc1xxx.cfg]
|
source [find target/xmc1xxx.cfg]
|
||||||
|
|
||||||
reset_config srst_only srst_nogate
|
reset_config srst_only srst_nogate
|
||||||
|
|
|
||||||
|
|
@ -9,6 +9,7 @@ source [find interface/jlink.cfg]
|
||||||
transport select swd
|
transport select swd
|
||||||
|
|
||||||
set CHIPNAME xmc1100
|
set CHIPNAME xmc1100
|
||||||
|
set WORKAREASIZE 0x4000
|
||||||
source [find target/xmc1xxx.cfg]
|
source [find target/xmc1xxx.cfg]
|
||||||
|
|
||||||
reset_config srst_only srst_nogate
|
reset_config srst_only srst_nogate
|
||||||
|
|
|
||||||
|
|
@ -24,4 +24,17 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID
|
||||||
set _TARGETNAME $_CHIPNAME.cpu
|
set _TARGETNAME $_CHIPNAME.cpu
|
||||||
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
|
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
|
||||||
|
|
||||||
|
if { [info exists WORKAREASIZE] } {
|
||||||
|
set _WORKAREASIZE $WORKAREASIZE
|
||||||
|
} else {
|
||||||
|
set _WORKAREASIZE 0x4000
|
||||||
|
}
|
||||||
|
|
||||||
|
$_TARGETNAME configure -work-area-phys 0x20000000 \
|
||||||
|
-work-area-size $_WORKAREASIZE \
|
||||||
|
-work-area-backup 0
|
||||||
|
|
||||||
|
set _FLASHNAME $_CHIPNAME.flash
|
||||||
|
flash bank $_FLASHNAME xmc1xxx 0x10000000 0 0 0 $_TARGETNAME
|
||||||
|
|
||||||
adapter_khz 1000
|
adapter_khz 1000
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue