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cortex_a: force cache and tlb bypass when cpu is in debug state 

for minimal impact on the hardware state, force all memory accesses to
bypass the caches and tlbs. This may actually be the default, but ARM
recommends in DDI0406C to set proper default values on debug init.

Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3079
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
__archive__
Matthias Welwarsky 2015-10-29 13:09:29 +01:00 committed by Paul Fertser
parent 6d7f5be6ac
commit 442e2506b1
2 changed files with 13 additions and 0 deletions
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1
src/target/armv7a.h
View File

@ -172,6 +172,7 @@ target_to_armv7a(struct target *target)
/* See ARMv7a arch spec section C10.7 */
#define CPUDBG_DSCCR 0x028
#define CPUDBG_DSMCR 0x02C
/* See ARMv7a arch spec section C10.8 */
#define CPUDBG_AUTHSTATUS 0xFB8

12
src/target/cortex_a.c
View File

@ -243,6 +243,18 @@ static int cortex_a_init_debug_access(struct target *target)
if (retval != ERROR_OK)
return retval;
/* Disable cacheline fills and force cache write-through in debug state */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSCCR, 0);
if (retval != ERROR_OK)
return retval;
/* Disable TLB lookup and refill/eviction in debug state */
retval = mem_ap_sel_write_atomic_u32(swjdp, armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DSMCR, 0);
if (retval != ERROR_OK)
return retval;
/* Enabling of instruction execution in debug mode is done in debug_entry code */
/* Resync breakpoint registers */