riscv: Correct DPC masking in compliance test.
parent
e32a8c911d
commit
434fb3708a
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@ -2413,8 +2413,8 @@ int riscv013_test_compliance(struct target *target) {
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uint64_t testvar64 = 0xAAAAAAAAAAAAAAAAUL;
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uint64_t testvar64 = 0xAAAAAAAAAAAAAAAAUL;
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uint64_t dpcmask = 0xFFFFFFFFFFFFFFFFUL;
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uint64_t dpcmask = 0xFFFFFFFFFFFFFFFFUL;
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riscv_set_register(target, GDB_REGNO_DPC, dpcmask);
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riscv_set_register(target, GDB_REGNO_DPC, dpcmask);
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dpcmask = riscv_get_register(target, GDB_REGNO_PC);
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dpcmask = riscv_get_register(target, GDB_REGNO_DPC);
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COMPLIANCE_TEST(dpcmask >= 0xFFFFFFFF, "DPC must hold at least 32 bits (may hold more but hard to tell how many)");
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COMPLIANCE_TEST(dpcmask >= 0xFFFFFFFC, "DPC must hold the minimum for a virtual address (may tighten requirement later).");
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riscv_set_register(target, GDB_REGNO_DPC, testvar64);
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riscv_set_register(target, GDB_REGNO_DPC, testvar64);
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COMPLIANCE_TEST((riscv_get_register(target, GDB_REGNO_DPC) & dpcmask) == (testvar64 & dpcmask), "DPC must be writable.");
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COMPLIANCE_TEST((riscv_get_register(target, GDB_REGNO_DPC) & dpcmask) == (testvar64 & dpcmask), "DPC must be writable.");
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riscv_set_register(target, GDB_REGNO_DPC, ~testvar64);
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riscv_set_register(target, GDB_REGNO_DPC, ~testvar64);
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