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aarch64: fix cache identification 

Use correct instructions to access CLIDR, CSSELR and CCSIDR.

Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
gitignore-build
Matthias Welwarsky 2016-09-16 11:49:57 +02:00
parent 7eb95b1d72
commit 4314624669
2 changed files with 18 additions and 28 deletions
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2
src/target/aarch64.c
View File

@ -1235,10 +1235,8 @@ static int aarch64_post_debug_entry(struct target *target)
LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg); LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
aarch64->system_control_reg_curr = aarch64->system_control_reg; aarch64->system_control_reg_curr = aarch64->system_control_reg;
#if 0
if (armv8->armv8_mmu.armv8_cache.ctype == -1) if (armv8->armv8_mmu.armv8_cache.ctype == -1)
armv8_identify_cache(target); armv8_identify_cache(target);
#endif
armv8->armv8_mmu.mmu_enabled = armv8->armv8_mmu.mmu_enabled =
(aarch64->system_control_reg & 0x1U) ? 1 : 0; (aarch64->system_control_reg & 0x1U) ? 1 : 0;

26
src/target/armv8.c
View File

@ -641,7 +641,6 @@ int armv8_identify_cache(struct target *target)
uint32_t cache_selected, clidr; uint32_t cache_selected, clidr;
uint32_t cache_i_reg, cache_d_reg; uint32_t cache_i_reg, cache_d_reg;
struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache); struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
if (!armv8->is_armv7r)
armv8_read_ttbcr(target); armv8_read_ttbcr(target);
retval = dpm->prepare(dpm); retval = dpm->prepare(dpm);
@ -650,7 +649,7 @@ int armv8_identify_cache(struct target *target)
/* retrieve CLIDR /* retrieve CLIDR
* mrc p15, 1, r0, c0, c0, 1 @ read clidr */ * mrc p15, 1, r0, c0, c0, 1 @ read clidr */
retval = dpm->instr_read_data_r0(dpm, retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(15, 1, 0, 0, 0, 1), ARMV8_MRS(SYSTEM_CLIDR, 0),
&clidr); &clidr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
@ -661,25 +660,18 @@ int armv8_identify_cache(struct target *target)
/* in cortex A7, A15 */ /* in cortex A7, A15 */
LOG_ERROR("cache l2 present :not supported"); LOG_ERROR("cache l2 present :not supported");
} }
/* retrieve selected cache /* retrieve selected cache*/
* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
retval = dpm->instr_read_data_r0(dpm, retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(15, 2, 0, 0, 0, 0), ARMV8_MRS(SYSTEM_CSSELR, 0),
&cache_selected); &cache_selected);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
retval = armv8->arm.mrc(target, 15,
2, 0, /* op1, op2 */
0, 0, /* CRn, CRm */
&cache_selected);
if (retval != ERROR_OK)
goto done;
/* select instruction cache /* select instruction cache
* MCR p15, 2,<Rd>, c0, c0, 0; Write CSSELR
* [0] : 1 instruction cache selection , 0 data cache selection */ * [0] : 1 instruction cache selection , 0 data cache selection */
retval = dpm->instr_write_data_r0(dpm, retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MRC(15, 2, 0, 0, 0, 0), ARMV8_MRS(SYSTEM_CSSELR, 0),
1); 1);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
@ -689,27 +681,27 @@ int armv8_identify_cache(struct target *target)
* [2:0] line size 001 eight word per line * [2:0] line size 001 eight word per line
* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */ * [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
retval = dpm->instr_read_data_r0(dpm, retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(15, 1, 0, 0, 0, 0), ARMV8_MRS(SYSTEM_CCSIDR, 0),
&cache_i_reg); &cache_i_reg);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
/* select data cache*/ /* select data cache*/
retval = dpm->instr_write_data_r0(dpm, retval = dpm->instr_write_data_r0(dpm,
ARMV4_5_MRC(15, 2, 0, 0, 0, 0), ARMV8_MRS(SYSTEM_CSSELR, 0),
0); 0);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
retval = dpm->instr_read_data_r0(dpm, retval = dpm->instr_read_data_r0(dpm,
ARMV4_5_MRC(15, 1, 0, 0, 0, 0), ARMV8_MRS(SYSTEM_CCSIDR, 0),
&cache_d_reg); &cache_d_reg);
if (retval != ERROR_OK) if (retval != ERROR_OK)
goto done; goto done;
/* restore selected cache */ /* restore selected cache */
dpm->instr_write_data_r0(dpm, dpm->instr_write_data_r0(dpm,
ARMV4_5_MRC(15, 2, 0, 0, 0, 0), ARMV8_MRS(SYSTEM_CSSELR, 0),
cache_selected); cache_selected);
if (retval != ERROR_OK) if (retval != ERROR_OK)