From 41c42bf2df4433b5a81e455ad5719317904ba4ca Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Thu, 17 May 2018 18:01:00 -0700
Subject: [PATCH] Comment riscv_set_register, register_write_direct

Fixes #241

Change-Id: Ia199f15106a0bda465d3918d052ddd4d03655031
---
 src/target/riscv/riscv-013.c | 4 ++++
 src/target/riscv/riscv.c     | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index b150b137f..12194d6d7 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1056,6 +1056,10 @@ static unsigned register_size(struct target *target, unsigned number)
 		return riscv_xlen(target);
 }
 
+/**
+ * Immediately write the new value to the requested register. This mechanism
+ * bypasses any caches.
+ */
 static int register_write_direct(struct target *target, unsigned number,
 		uint64_t value)
 {
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index b1714698c..c599ef2ea 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1763,6 +1763,10 @@ bool riscv_has_register(struct target *target, int hartid, int regid)
 	return 1;
 }
 
+/**
+ * This function is called when the debug user wants to change the value of a
+ * register. The new value may be cached, and may not be written until the hart
+ * is running again. */
 int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v)
 {
 	return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v);