Blind coding new dbus behavior.
Tim Newsome
parent
feff2dd9e7
commit
413ab49dfd
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@ -20,38 +20,55 @@
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/*** JTAG registers. ***/
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#define DTMINFO 0x10
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#define DTMINFO_ADDRBITS (0xf<<4)
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#define DTMINFO_VERSION (0xf)
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#define DTMINFO 0x10
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#define DTMINFO_ADDRBITS (0xf<<4)
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#define DTMINFO_VERSION (0xf)
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#define DBUS 0x11
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#define DBUS 0x11
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#define DBUS_OP_START 0
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#define DBUS_OP_SIZE 2
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typedef enum {
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DBUS_OP_NOP = 0,
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DBUS_OP_READ = 1,
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DBUS_OP_WRITE = 2,
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DBUS_OP_CONDITIONAL_WRITE = 3
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} dbus_op_t;
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typedef enum {
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DBUS_RESULT_SUCCESS = 0,
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DBUS_RESULT_NO_WRITE = 1,
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DBUS_RESULT_FAILED = 2,
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DBUS_RESULT_BUSY = 3
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} dbus_result_t;
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#define DBUS_DATA_START 2
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#define DBUS_DATA_SIZE 34
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#define DBUS_ADDRESS_START 36
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/*** Debug Bus registers. ***/
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#define DMCONTROL 0x10
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#define DMCONTROL_HALTNOT (1L<<33)
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#define DMCONTROL_INTERRUPT (1L<<32)
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#define DMCONTROL_BUSERROR (7<<19)
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#define DMCONTROL_SERIAL (3<<16)
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#define DMCONTROL 0x10
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#define DMCONTROL_HALTNOT (1L<<33)
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#define DMCONTROL_INTERRUPT (1L<<32)
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#define DMCONTROL_BUSERROR (7<<19)
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#define DMCONTROL_SERIAL (3<<16)
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#define DMCONTROL_AUTOINCREMENT (1<<15)
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#define DMCONTROL_ACCESS (7<<12)
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#define DMCONTROL_HARTID (0x3ff<<2)
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#define DMCONTROL_NDRESET (1<<1)
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#define DMCONTROL_FULLRESET 1
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#define DMCONTROL_ACCESS (7<<12)
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#define DMCONTROL_HARTID (0x3ff<<2)
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#define DMCONTROL_NDRESET (1<<1)
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#define DMCONTROL_FULLRESET 1
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#define DMINFO 0x11
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#define DMINFO_ABUSSIZE (0x7f<<25)
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#define DMINFO_SERIALCOUNT (0xf<<21)
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#define DMINFO_ACCESS128 (1<<20)
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#define DMINFO_ACCESS64 (1<<19)
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#define DMINFO_ACCESS32 (1<<18)
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#define DMINFO_ACCESS16 (1<<17)
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#define DMINFO_ACCESS8 (1<<16)
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#define DMINFO_DRAMSIZE (0x3f<<10)
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#define DMINFO 0x11
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#define DMINFO_ABUSSIZE (0x7f<<25)
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#define DMINFO_SERIALCOUNT (0xf<<21)
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#define DMINFO_ACCESS128 (1<<20)
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#define DMINFO_ACCESS64 (1<<19)
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#define DMINFO_ACCESS32 (1<<18)
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#define DMINFO_ACCESS16 (1<<17)
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#define DMINFO_ACCESS8 (1<<16)
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#define DMINFO_DRAMSIZE (0x3f<<10)
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#define DMINFO_AUTHENTICATED (1<<5)
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#define DMINFO_AUTHBUSY (1<<4)
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#define DMINFO_AUTHTYPE (3<<2)
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#define DMINFO_VERSION 3
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#define DMINFO_AUTHBUSY (1<<4)
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#define DMINFO_AUTHTYPE (3<<2)
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#define DMINFO_VERSION 3
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/*** Info about the core being debugged. ***/
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@ -65,6 +82,8 @@ typedef struct {
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/* Last value we wrote to DBUS_ADDRESS (eg. the address of the register
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* whose value will be read the next time we scan dbus). */
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uint16_t dbus_address;
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/* Last op we wrote to dbus. */
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dbus_op_t dbus_op;
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/* Number of words in Debug RAM. */
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unsigned int dramsize;
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/* Our local copy of Debug RAM. */
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@ -78,18 +97,26 @@ typedef struct {
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/*** Utility functions. ***/
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static uint8_t ir_dtminfo[1] = {DTMINFO};
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static struct scan_field scan_dtminfo = {
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static struct scan_field select_dtminfo = {
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.in_value = NULL,
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.out_value = ir_dtminfo
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};
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static uint8_t ir_dbus[1] = {DBUS};
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static struct scan_field scan_dbus = {
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static struct scan_field select_dbus = {
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.in_value = NULL,
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.out_value = ir_dbus
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};
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static uint64_t dbus_scan(struct target *target, uint16_t address,
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uint64_t data_out, bool read, bool write)
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static uint16_t dram_address(unsigned int index)
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{
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if (index < 0x10)
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return index;
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else
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return 0x40 + index - 0x10;
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}
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static dbus_result_t dbus_scan(struct target *target, uint64_t *data_in,
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dbus_op_t op, uint16_t address, uint64_t data_out)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct scan_field field;
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@ -98,17 +125,17 @@ static uint64_t dbus_scan(struct target *target, uint16_t address,
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assert(info->addrbits != 0);
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// TODO: max bits is 32?
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field.num_bits = info->addrbits + 35;
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field.num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
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field.out_value = out;
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field.in_value = in;
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buf_set_u64(out, 0, 34, data_out);
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buf_set_u64(out, 34, info->addrbits, address);
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buf_set_u64(out, info->addrbits + 34, 1, write);
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buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
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buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
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buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address);
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/* Assume dbus is already selected. */
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jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
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info->dbus_address = address;
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info->dbus_op = op;
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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@ -116,22 +143,43 @@ static uint64_t dbus_scan(struct target *target, uint16_t address,
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return retval;
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}
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return buf_get_u64(in, 0, 34);
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if (data_in) {
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*data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
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}
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return buf_get_u64(in, DBUS_OP_START, DBUS_OP_SIZE);
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}
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static uint64_t dbus_read(struct target *target, uint16_t address, uint16_t next_address)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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uint64_t value;
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if (address != info->dbus_address) {
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dbus_scan(target, address, 0, false, false);
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dbus_result_t result = DBUS_RESULT_BUSY;
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if (address != info->dbus_address || info->dbus_op == DBUS_OP_NOP) {
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while (result == DBUS_RESULT_BUSY) {
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result = dbus_scan(target, NULL, DBUS_OP_READ, address, 0);
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}
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}
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return dbus_scan(target, next_address, 0, true, false);
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result = DBUS_RESULT_BUSY;
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while (result == DBUS_RESULT_BUSY) {
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result = dbus_scan(target, &value, DBUS_OP_READ, next_address, 0);
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}
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if (result != DBUS_RESULT_SUCCESS) {
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LOG_ERROR("dbus_read failed read at 0x%x; result=%d\n", address, result);
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}
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return value;
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}
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static uint64_t dbus_write(struct target *target, uint16_t address, uint64_t value)
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static void dbus_write(struct target *target, uint16_t address, uint64_t value)
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{
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return dbus_scan(target, address, value, false, true);
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dbus_result_t result = DBUS_RESULT_BUSY;
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while (result == DBUS_RESULT_BUSY) {
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result = dbus_scan(target, NULL, DBUS_OP_WRITE, address, value);
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}
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if (result != DBUS_RESULT_SUCCESS) {
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LOG_ERROR("dbus_write failed write 0x%lx to 0x%x; result=%d\n", value,
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address, result);
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}
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}
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static uint32_t dtminfo_read(struct target *target)
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@ -139,7 +187,7 @@ static uint32_t dtminfo_read(struct target *target)
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struct scan_field field;
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uint8_t in[4];
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jtag_add_ir_scan(target->tap, &scan_dtminfo, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &select_dtminfo, TAP_IDLE);
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field.num_bits = 32;
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field.out_value = NULL;
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@ -148,7 +196,7 @@ static uint32_t dtminfo_read(struct target *target)
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("dbus_scan failed jtag scan");
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LOG_ERROR("dtminfo_read failed jtag scan");
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return retval;
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}
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@ -156,24 +204,37 @@ static uint32_t dtminfo_read(struct target *target)
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/* TODO: Can we rely on IR not being messed with between calls into
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* RISCV code? Eg. what happens if there are multiple cores and some
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* other core is accessed? */
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jtag_add_ir_scan(target->tap, &scan_dbus, TAP_IDLE);
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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return buf_get_u32(field.in_value, 0, 32);
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}
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static uint32_t dram_read32(struct target *target, unsigned int index,
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bool set_interrupt)
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{
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// TODO: check cache to see if this even needs doing.
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uint16_t address = dram_address(index);
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return dbus_read(target, address, address);
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}
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static void dram_write32(struct target *target, unsigned int index, uint32_t value,
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bool set_interrupt)
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{
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// TODO: check cache to see this even needs doing.
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uint16_t address;
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if (index < 0x10)
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address = index;
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else
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address = 0x40 + index - 0x10;
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// TODO: check cache to see if this even needs doing.
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uint64_t dbus_value = DMCONTROL_HALTNOT | value;
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if (set_interrupt)
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dbus_value |= DMCONTROL_INTERRUPT;
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dbus_write(target, address, dbus_value);
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dbus_write(target, dram_address(index), dbus_value);
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}
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static void dram_check32(struct target *target, unsigned int index,
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uint32_t expected)
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{
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uint32_t actual = dram_read32(target, index, false);
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if (expected != actual) {
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LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
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expected, index, actual);
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}
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}
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/* Write instruction that jumps from the specified word in Debug RAM to resume
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@ -196,9 +257,10 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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return ERROR_FAIL;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->dbus_address = DBUS_ADDRESS_UNKNOWN;
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info->dbus_op = DBUS_OP_NOP;
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scan_dtminfo.num_bits = target->tap->ir_length;
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scan_dbus.num_bits = target->tap->ir_length;
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select_dtminfo.num_bits = target->tap->ir_length;
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select_dbus.num_bits = target->tap->ir_length;
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return ERROR_OK;
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}
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@ -254,6 +316,13 @@ static int riscv_examine(struct target *target)
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 5, true);
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// Check that we can actually read/write dram.
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dram_check32(target, 0, xori(S1, ZERO, -1));
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dram_check32(target, 1, srli(S1, S1, 31));
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dram_check32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
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dram_check32(target, 3, srli(S1, S1, 31));
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dram_check32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
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target_set_examined(target);
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return ERROR_OK;
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