- integrated patch from Magnus Lundin that fixes at91sam7 flash timing bugs and possible endianness problems (big endian hosts)
- correctly write trailing bytes on str7x flashes - speed up str7x flash writing by offloading the algorithm to the target git-svn-id: svn://svn.berlios.de/openocd/trunk@95 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
drath
parent
028f59ede5
commit
3f74f764c7
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@ -135,8 +135,7 @@ u32 at91sam7_get_flash_status(flash_bank_t *bank)
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target_t *target = at91sam7_info->target;
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u32 fsr;
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target->type->read_memory(target, MC_FSR, 4, 1, (u8 *)&fsr);
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fsr = target_buffer_get_u32(target, (u8 *)&fsr);
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target_read_u32(target, MC_FSR, &fsr);
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return fsr;
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}
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@ -146,19 +145,15 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
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{
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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target_t *target = at91sam7_info->target;
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unsigned long mckr, mcfr, pllr, tmp, status, mainfreq;
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unsigned int css, pres, mul, div;
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u32 mckr, mcfr, pllr;
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unsigned long tmp, mainfreq;
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/* Read main clock freqency register */
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target->type->read_memory(target, CKGR_MCFR, 4, 1, (u8 *)&mcfr);
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target_read_u32(target, CKGR_MCFR, &mcfr);
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/* Read master clock register */
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target->type->read_memory(target, PMC_MCKR, 4, 1, (u8 *)&mckr);
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target_read_u32(target, PMC_MCKR, &mckr);
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/* Read Clock Generator PLL Register */
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target->type->read_memory(target, CKGR_PLLR, 4, 1, (u8 *)&pllr);
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pres = (mckr>>2)&0x7;
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mul = (pllr>>16)&0x7FF;
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div = pllr&0xFF;
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target_read_u32(target, CKGR_PLLR, &pllr);
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at91sam7_info->mck_valid = 0;
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switch (mckr & PMC_MCKR_CSS) {
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@ -180,8 +175,7 @@ void at91sam7_read_clock_info(flash_bank_t *bank)
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case 3: /* PLL Clock */
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if (mcfr & CKGR_MCFR_MAINRDY)
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{
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target->type->read_memory(target, CKGR_PLLR, 4, 1,
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(u8 *)&pllr);
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target_read_u32(target, CKGR_PLLR, &pllr);
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if (!(pllr & CKGR_PLLR_DIV))
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break; /* 0 Hz */
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at91sam7_info->mck_valid = 1;
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@ -211,7 +205,8 @@ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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target_t *target = at91sam7_info->target;
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if (mode && (mode != at91sam7_info->flashmode)) {
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if (mode && (mode != at91sam7_info->flashmode))
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{
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/* Always round up (ceil) */
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if (mode==1)
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/* main clocks in 1uS */
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@ -220,16 +215,18 @@ void at91sam7_set_flash_mode(flash_bank_t *bank,int mode)
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/* main clocks in 1.5uS */
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fmcn = (at91sam7_info->mck_freq/666666ul)+1;
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/* Only allow fmcn=0 if clock period is > 30 us. */
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if (at91sam7_info->mck_freq <= 33333333ul)
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/* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
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if (at91sam7_info->mck_freq <= 33333ul)
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fmcn = 0;
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else
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/* Only allow fws=0 if clock frequency is < 30 MHz. */
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if (at91sam7_info->mck_freq > 30000000ul)
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fws = 1;
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DEBUG("fmcn: %i", fmcn);
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fmr = fmcn << 16 | fws << 8;
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target->type->write_memory(target, MC_FMR, 4, 1, (u8 *)&fmr);
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target_write_u32(target, MC_FMR, fmr);
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}
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at91sam7_info->flashmode = mode;
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}
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@ -267,7 +264,7 @@ int at91sam7_flash_command(struct flash_bank_s *bank,u8 cmd,u16 pagen)
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target_t *target = at91sam7_info->target;
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fcr = (0x5A<<24) | (pagen<<8) | cmd;
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target->type->write_memory(target, MC_FCR, 4, 1, (u8 *)&fcr);
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target_write_u32(target, MC_FCR, fcr);
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DEBUG("Flash command: 0x%x, pagenumber:", fcr, pagen);
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if (at91sam7_wait_status_busy(bank, 10)&0x0C)
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@ -282,7 +279,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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{
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at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
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target_t *target = at91sam7_info->target;
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unsigned long cidr, mcfr, status;
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u32 cidr, status;
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if (at91sam7_info->target->state != TARGET_HALTED)
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{
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@ -290,7 +287,7 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
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}
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/* Read and parse chip identification register */
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target->type->read_memory(target, DBGU_CIDR, 4, 1, (u8 *)&cidr);
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target_read_u32(target, DBGU_CIDR, &cidr);
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if (cidr == 0)
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{
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@ -496,7 +493,6 @@ int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, ch
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exit(-1);
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}
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/* part wasn't probed for info yet */
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at91sam7_info->cidr = 0;
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@ -685,6 +681,7 @@ int at91sam7_probe(struct flash_bank_s *bank)
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WARNING("Cannot identify target as an AT91SAM");
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return ERROR_FLASH_OPERATION_FAILED;
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}
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return ERROR_OK;
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}
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@ -1003,11 +1003,11 @@ int cfi_erase_check(struct flash_bank_s *bank)
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{
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u32 erase_check_code[] =
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{
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0xe4d03001,
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0xe0022003,
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0xe2511001,
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0x1afffffb,
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0xeafffffe
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0xe4d03001, /* ldrb r3, [r0], #1 */
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0xe0022003, /* and r2, r2, r3 */
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0xe2511001, /* subs r1, r1, #1 */
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0x1afffffb, /* b -4 */
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0xeafffffe /* b 0 */
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};
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/* make sure we have a working area */
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@ -1017,8 +1017,13 @@ int cfi_erase_check(struct flash_bank_s *bank)
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}
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else
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{
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u8 erase_check_code_buf[5 * 4];
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for (i = 0; i < 5; i++)
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target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
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/* write algorithm code to working area */
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target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, (u8*)erase_check_code);
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target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
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}
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}
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@ -25,6 +25,7 @@
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#include "command.h"
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#include "log.h"
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#include "target.h"
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#include "time_support.h"
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#include <string.h>
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#include <unistd.h>
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@ -526,6 +527,8 @@ int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, cha
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if ((retval = p->driver->write(p, buffer, offset, buf_cnt)) != ERROR_OK)
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{
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command_print(cmd_ctx, "failed writing file %s to flash bank %i at offset 0x%8.8x",
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args[1], strtoul(args[0], NULL, 0), strtoul(args[2], NULL, 0));
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switch (retval)
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{
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case ERROR_TARGET_NOT_HALTED:
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@ -553,14 +556,16 @@ int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, cha
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command_print(cmd_ctx, "unknown error");
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}
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}
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free(buffer);
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fclose(binary);
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else
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{
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gettimeofday(&end, NULL);
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timeval_subtract(&duration, &end, &start);
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command_print(cmd_ctx, "wrote file %s to flash bank %i at offset 0x%8.8x in %is %ius", args[1], strtoul(args[0], NULL, 0), strtoul(args[2], NULL, 0), duration.tv_sec, duration.tv_usec);
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}
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free(buffer);
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fclose(binary);
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return ERROR_OK;
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}
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@ -172,6 +172,8 @@ int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char
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str7x_build_block_list(bank);
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str7x_info->write_algorithm = NULL;
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return ERROR_OK;
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}
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@ -181,7 +183,7 @@ u32 str7x_status(struct flash_bank_s *bank)
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target_t *target = str7x_info->target;
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u32 retval;
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target->type->read_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&retval);
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target_read_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), &retval);
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return retval;
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}
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@ -192,7 +194,7 @@ u32 str7x_result(struct flash_bank_s *bank)
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target_t *target = str7x_info->target;
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u32 retval;
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target->type->read_memory(target, str7x_get_flash_adr(bank, FLASH_ER), 4, 1, (u8*)&retval);
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target_read_u32(target, str7x_get_flash_adr(bank, FLASH_ER), &retval);
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return retval;
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}
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@ -242,14 +244,14 @@ int str7x_protect_check(struct flash_bank_s *bank)
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target_t *target = str7x_info->target;
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int i;
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int retval;
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u32 retval;
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if (str7x_info->target->state != TARGET_HALTED)
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{
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return ERROR_TARGET_NOT_HALTED;
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}
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target->type->read_memory(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), 4, 1, (u8*)&retval);
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target_read_u32(target, str7x_get_flash_adr(bank, FLASH_NVWPAR), &retval);
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for (i = 0; i < bank->num_sectors; i++)
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{
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@ -282,14 +284,17 @@ int str7x_erase(struct flash_bank_s *bank, int first, int last)
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for (i = first; i <= last; i++)
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erase_blocks |= (mem_layout[i].reg_offset << i);
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/* clear FLASH_ER register */
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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cmd = FLASH_SER;
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target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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cmd = erase_blocks;
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target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR1), 4, 1, (u8*)&cmd);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR1), cmd);
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cmd = FLASH_SER|FLASH_WMS;
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target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
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usleep(1000);
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@ -330,17 +335,20 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
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protect_blocks &= ~(mem_layout[i].reg_offset << i);
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}
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/* clear FLASH_ER register */
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
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cmd = FLASH_SPR;
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target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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cmd = str7x_get_flash_adr(bank, FLASH_NVWPAR);
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target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_AR), 4, 1, (u8*)&cmd);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), cmd);
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cmd = protect_blocks;
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target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, (u8*)&cmd);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), cmd);
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cmd = FLASH_SPR|FLASH_WMS;
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target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
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target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
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while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
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usleep(1000);
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@ -348,6 +356,8 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
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retval = str7x_result(bank);
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DEBUG("retval: 0x%8.8x", retval);
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if (retval & FLASH_ERER)
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return ERROR_FLASH_SECTOR_NOT_ERASED;
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else if (retval & FLASH_WPF)
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@ -356,6 +366,123 @@ int str7x_protect(struct flash_bank_s *bank, int set, int first, int last)
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return ERROR_OK;
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}
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int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
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{
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str7x_flash_bank_t *str7x_info = bank->driver_priv;
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target_t *target = str7x_info->target;
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u32 buffer_size = 8192;
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working_area_t *source;
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u32 address = bank->base + offset;
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reg_param_t reg_params[5];
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armv4_5_algorithm_t armv4_5_info;
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int retval;
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u32 str7x_flash_write_code[] = {
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/* write: */
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0xe3a04201, /* mov r4, #0x10000000 */
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0xe5824000, /* str r4, [r2, #0x0] */
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0xe5821010, /* str r1, [r2, #0x10] */
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0xe4904004, /* ldr r4, [r0], #4 */
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0xe5824008, /* str r4, [r2, #0x8] */
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0xe4904004, /* ldr r4, [r0], #4 */
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0xe582400c, /* str r4, [r2, #0xc] */
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0xe3a04209, /* mov r4, #0x90000000 */
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0xe5824000, /* str r4, [r2, #0x0] */
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/* busy: */
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0xe5924000, /* ldr r4, [r2, #0x0] */
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0xe3140016, /* tst r4, #0x16 */
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0x1afffffc, /* bne busy */
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0xe5924014, /* ldr r4, [r2, #0x14] */
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0xe31400ff, /* tst r4, #0xff */
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0x03140c01, /* tsteq r4, #0x100 */
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0x1a000002, /* bne exit */
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0xe2811008, /* add r1, r1, #0x8 */
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0xe2533001, /* subs r3, r3, #1 */
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0x1affffec, /* bne write */
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/* exit: */
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0xeafffffe, /* b exit */
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};
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u8 str7x_flash_write_code_buf[80];
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int i;
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/* flash write code */
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if (!str7x_info->write_algorithm)
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{
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if (target_alloc_working_area(target, 4 * 20, &str7x_info->write_algorithm) != ERROR_OK)
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{
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WARNING("no working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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};
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/* convert flash writing code into a buffer in target endianness */
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for (i = 0; i < 20; i++)
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target_buffer_set_u32(target, str7x_flash_write_code_buf + i*4, str7x_flash_write_code[i]);
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target_write_buffer(target, str7x_info->write_algorithm->address, 20 * 4, str7x_flash_write_code_buf);
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}
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/* memory buffer */
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while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
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{
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buffer_size /= 2;
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if (buffer_size <= 256)
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{
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/* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
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if (str7x_info->write_algorithm)
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target_free_working_area(target, str7x_info->write_algorithm);
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WARNING("no large enough working area available, can't do block memory writes");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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};
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armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
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init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
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init_reg_param(®_params[4], "r4", 32, PARAM_IN);
|
||||
|
||||
while (count > 0)
|
||||
{
|
||||
u32 thisrun_count = (count > (buffer_size / 8)) ? (buffer_size / 8) : count;
|
||||
|
||||
target_write_buffer(target, source->address, thisrun_count * 8, buffer);
|
||||
|
||||
buf_set_u32(reg_params[0].value, 0, 32, source->address);
|
||||
buf_set_u32(reg_params[1].value, 0, 32, address);
|
||||
buf_set_u32(reg_params[2].value, 0, 32, str7x_get_flash_adr(bank, FLASH_CR0));
|
||||
buf_set_u32(reg_params[3].value, 0, 32, thisrun_count);
|
||||
|
||||
if ((retval = target->type->run_algorithm(target, 0, NULL, 5, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
|
||||
{
|
||||
ERROR("error executing str7x flash write algorithm");
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
|
||||
{
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
buffer += thisrun_count * 8;
|
||||
address += thisrun_count * 8;
|
||||
count -= thisrun_count;
|
||||
}
|
||||
|
||||
destroy_reg_param(®_params[0]);
|
||||
destroy_reg_param(®_params[1]);
|
||||
destroy_reg_param(®_params[2]);
|
||||
destroy_reg_param(®_params[3]);
|
||||
destroy_reg_param(®_params[4]);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
||||
{
|
||||
str7x_flash_bank_t *str7x_info = bank->driver_priv;
|
||||
|
|
@ -363,44 +490,80 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
|||
u32 dwords_remaining = (count / 8);
|
||||
u32 bytes_remaining = (count & 0x00000007);
|
||||
u32 address = bank->base + offset;
|
||||
u32 *wordbuffer = (u32*)buffer;
|
||||
u32 bytes_written = 0;
|
||||
u32 cmd;
|
||||
u32 retval;
|
||||
|
||||
|
||||
if (str7x_info->target->state != TARGET_HALTED)
|
||||
{
|
||||
return ERROR_TARGET_NOT_HALTED;
|
||||
}
|
||||
|
||||
if (offset & 0x7)
|
||||
{
|
||||
WARNING("offset 0x%x breaks required 8-byte alignment", offset);
|
||||
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
|
||||
}
|
||||
|
||||
if (offset + count > bank->size)
|
||||
return ERROR_FLASH_DST_OUT_OF_BANK;
|
||||
|
||||
/* clear FLASH_ER register */
|
||||
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
|
||||
|
||||
/* multiple dwords (8-byte) to be programmed? */
|
||||
if (dwords_remaining > 0)
|
||||
{
|
||||
/* try using a block write */
|
||||
if ((retval = str7x_write_block(bank, buffer, offset, dwords_remaining)) != ERROR_OK)
|
||||
{
|
||||
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
|
||||
{
|
||||
/* if block write failed (no sufficient working area),
|
||||
* we use normal (slow) single dword accesses */
|
||||
WARNING("couldn't use block writes, falling back to single memory accesses");
|
||||
}
|
||||
else if (retval == ERROR_FLASH_OPERATION_FAILED)
|
||||
{
|
||||
/* if an error occured, we examine the reason, and quit */
|
||||
retval = str7x_result(bank);
|
||||
|
||||
ERROR("flash writing failed with error code: 0x%x", retval);
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
buffer += dwords_remaining * 8;
|
||||
address += dwords_remaining * 8;
|
||||
dwords_remaining = 0;
|
||||
}
|
||||
}
|
||||
|
||||
while (dwords_remaining > 0)
|
||||
{
|
||||
// command
|
||||
cmd = FLASH_DWPG;
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
|
||||
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
||||
|
||||
// address
|
||||
cmd = address;
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_AR), 4, 1, (u8*)&cmd);
|
||||
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
|
||||
|
||||
// data byte 1
|
||||
cmd = wordbuffer[bytes_written/4];
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, (u8*)&cmd);
|
||||
// data word 1
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, buffer + bytes_written);
|
||||
bytes_written += 4;
|
||||
|
||||
// data byte 2
|
||||
cmd = wordbuffer[bytes_written/4];
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, (u8*)&cmd);
|
||||
// data word 2
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, buffer + bytes_written);
|
||||
bytes_written += 4;
|
||||
|
||||
/* start programming cycle */
|
||||
cmd = FLASH_DWPG | FLASH_WMS;
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
|
||||
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
||||
|
||||
while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
|
||||
while (((retval = str7x_status(bank)) & (FLASH_BSYA1 | FLASH_BSYA2)))
|
||||
{
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
|
|
@ -415,25 +578,39 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
|||
address += 8;
|
||||
}
|
||||
|
||||
if (bytes_remaining)
|
||||
{
|
||||
u8 last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
|
||||
int i = 0;
|
||||
|
||||
while(bytes_remaining > 0)
|
||||
{
|
||||
last_dword[i++] = *(buffer + bytes_written);
|
||||
bytes_remaining--;
|
||||
bytes_written++;
|
||||
}
|
||||
|
||||
// command
|
||||
cmd = FLASH_WPG;
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
|
||||
cmd = FLASH_DWPG;
|
||||
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
||||
|
||||
// address
|
||||
cmd = address;
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_AR), 4, 1, (u8*)&cmd);
|
||||
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), address);
|
||||
|
||||
// data byte
|
||||
cmd = buffer[bytes_written];
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, (u8*)&cmd);
|
||||
// data word 1
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR0), 4, 1, last_dword);
|
||||
bytes_written += 4;
|
||||
|
||||
// data word 2
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_DR1), 4, 1, last_dword + 4);
|
||||
bytes_written += 4;
|
||||
|
||||
/* start programming cycle */
|
||||
cmd = FLASH_WPG|FLASH_WMS;
|
||||
target->type->write_memory(target, str7x_get_flash_adr(bank, FLASH_CR0), 4, 1, (u8*)&cmd);
|
||||
cmd = FLASH_DWPG | FLASH_WMS;
|
||||
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), cmd);
|
||||
|
||||
while (((retval = str7x_status(bank)) & (FLASH_BSYA1|FLASH_BSYA2))){
|
||||
while (((retval = str7x_status(bank)) & (FLASH_BSYA1 | FLASH_BSYA2)))
|
||||
{
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
|
|
@ -443,10 +620,6 @@ int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
|
|||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
else if (retval & FLASH_WPF)
|
||||
return ERROR_FLASH_OPERATION_FAILED;
|
||||
|
||||
address++;
|
||||
bytes_remaining--;
|
||||
bytes_written++;
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@ typedef struct str7x_flash_bank_s
|
|||
int bank1;
|
||||
struct target_s *target;
|
||||
u32 flash_base;
|
||||
working_area_t *write_algorithm;
|
||||
} str7x_flash_bank_t;
|
||||
|
||||
enum str7x_status_codes
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
|
||||
#define OPENOCD_VERSION "Open On-Chip Debugger (2006-08-31 15:00 CEST)"
|
||||
#define OPENOCD_VERSION "Open On-Chip Debugger (2006-09-07 20:00 CEST)"
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
|
|
|
|||
Loading…
Reference in New Issue