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flash/nor: add support for TI MSP432 devices 

Added msp432 flash driver to support the TI MSP432P4x and
MSP432E4x microcontrollers. Implemented the flash algo
helper as used in the TI debug and flash tools. This
implemention supports the MSP432E4, Falcon, and Falcon 2M
variants. The flash driver automatically detects the
connected variant and configures itself appropriately.
Added command to mass erase device for consistency with
TI tools and added command to unlock the protected BSL
region.

Tested using MSP432E401Y, MSP432P401R, and MSP432P4111
LaunchPads.
Tested with embedded XDS110 debug probe in CMSIS-DAP
mode and with external SEGGER J-Link probe.

Removed ti_msp432p4xx.cfg file made obsolete by this
patch.
Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0
Signed-off-by: Edward Fewell <efewell@ti.com>
Reviewed-on: http://openocd.zylin.com/4153
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
bscan_tunnel
Edward Fewell 2017-06-02 21:20:26 -05:00 committed by Tomas Vanek
parent b24301a01a
commit 3e84da55a6
26 changed files with 5657 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

126
contrib/loaders/flash/msp432/MSP432E4_FlashLibIf.h Normal file
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/******************************************************************************
*
* Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H
#define OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H
#include <stddef.h>
#include <stdint.h>
/* RAM loader */
static const uint32_t RAM_LOADER_START = 0x20000000u; /* Code space */
static const uint32_t RAM_LOADER_MAIN = 0x20000110u; /* Code space */
static const uint32_t RAM_LOADER_BUFFER1 = 0x20002000u; /* SBUS data space */
static const uint32_t RAM_LOADER_BUFFER2 = 0x20003000u; /* SBUS data space */
static const uint32_t RAM_LOADER_STACK = 0x20002000u; /* SBUS data space */
/* Address for flash function to be executed */
static const uint32_t FLASH_FUNCTION_ADDRESS = 0x20000150u;
enum flash_command {
FLASH_NO_COMMAND = 0,
FLASH_MASS_ERASE = 1,
FLASH_SECTOR_ERASE = 2,
FLASH_PROGRAM = 4,
FLASH_INIT = 8,
FLASH_EXIT = 16,
FLASH_CONTINUOUS_PROGRAM = 32
};
/* Address for algorithm program and flash buffer */
static const uint32_t DST_ADDRESS = 0x2000015Cu;
static const uint32_t SRC_LENGTH_ADDRESS = 0x20000160u;
static const uint32_t BUFFER1_STATUS_REGISTER = 0x20000164u;
static const uint32_t BUFFER2_STATUS_REGISTER = 0x20000168u;
static const uint32_t BUFFER_INACTIVE = 0x00000000u;
static const uint32_t BUFFER_ACTIVE = 0x00000001u;
static const uint32_t BUFFER_DATA_READY = 0x00000010u;
static const size_t SRC_LENGTH_MAX = 4096u;
/* Erase options */
static const uint32_t ERASE_PARAM_ADDRESS = 0x2000016Cu;
static const uint32_t ERASE_MAIN = 0x00000001u;
static const uint32_t ERASE_INFO = 0x00000002u;
/* Unlock BSL */
static const uint32_t UNLOCK_BSL_ADDRESS = 0x20000170u;
static const uint32_t LOCK_BSL_KEY = 0x00000000u;
static const uint32_t UNLOCK_BSL_KEY = 0x0000000Bu;
/* Address for return code */
static const uint32_t RETURN_CODE_ADDRESS = 0x20000154u;
/* Return codes */
static const uint32_t FLASH_BUSY = 0x00000001u;
static const uint32_t FLASH_SUCCESS = 0x00000ACEu;
static const uint32_t FLASH_ERROR = 0x0000DEADu;
static const uint32_t FLASH_TIMEOUT_ERROR = 0xDEAD0000u;
static const uint32_t FLASH_VERIFY_ERROR = 0xDEADDEADu;
static const uint32_t FLASH_WRONG_COMMAND = 0x00000BADu;
static const uint32_t FLASH_POWER_ERROR = 0x00DEAD00u;
/* Device ID address */
static const uint32_t DEVICE_ID_ADDRESS = 0x0020100Cu;
static const uint32_t PC_REGISTER = 15u;
static const uint32_t SP_REGISTER = 13u;
/* CS silicon and boot code revisions */
static const uint32_t SILICON_REV_ADDRESS = 0x00201010u;
static const uint32_t SILICON_REV_A = 0x00000041u;
static const uint32_t SILICON_REV_B = 0x00000042u;
static const uint32_t SILICON_REV_C = 0x00000043u;
static const uint32_t SILICON_REV_D = 0x00000044u;
static const uint32_t SILICON_REV_E = 0x00000045u;
static const uint32_t SILICON_REV_F = 0x00000046u;
static const uint32_t SILICON_REV_G = 0x00000047u;
static const uint32_t SILICON_REV_H = 0x00000048u;
static const uint32_t SILICON_REV_I = 0x00000049u;
static const uint32_t SILICON_REV_B_WRONG = 0x00004100u;
struct flash_interface {
volatile uint32_t FLASH_FUNCTION;
volatile uint32_t RETURN_CODE;
volatile uint32_t _RESERVED0;
volatile uint32_t DST_ADDRESS;
volatile uint32_t SRC_LENGTH;
volatile uint32_t BUFFER1_STATUS_REGISTER;
volatile uint32_t BUFFER2_STATUS_REGISTER;
volatile uint32_t ERASE_PARAM;
volatile uint32_t UNLOCK_BSL;
};
#define FLASH_LOADER_BASE ((uint32_t)0x20000150u)
#define FLASH_LOADER ((struct flash_interface *) FLASH_LOADER_BASE)
#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432E4_FLASHLIBIF_H */

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contrib/loaders/flash/msp432/MSP432P4_FlashLibIf.h Normal file
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/******************************************************************************
*
* Copyright (C) 2014-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H
#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H
#include <stddef.h>
#include <stdint.h>
/* RAM loader */
static const uint32_t RAM_LOADER_START = 0x01000000u; /* Code space */
static const uint32_t RAM_LOADER_MAIN = 0x01000110u; /* Code space */
static const uint32_t RAM_LOADER_BUFFER1 = 0x20002000u; /* SBUS data space */
static const uint32_t RAM_LOADER_BUFFER2 = 0x20003000u; /* SBUS data space */
static const uint32_t RAM_LOADER_STACK = 0x20002000u; /* SBUS data space */
/* Address for flash function to be executed */
static const uint32_t FLASH_FUNCTION_ADDRESS = 0x20000150u;
enum flash_command {
FLASH_NO_COMMAND = 0,
FLASH_MASS_ERASE = 1,
FLASH_SECTOR_ERASE = 2,
FLASH_PROGRAM = 4,
FLASH_INIT = 8,
FLASH_EXIT = 16,
FLASH_CONTINUOUS_PROGRAM = 32
};
/* Address for algorithm program and flash buffer */
static const uint32_t DST_ADDRESS = 0x2000015Cu;
static const uint32_t SRC_LENGTH_ADDRESS = 0x20000160u;
static const uint32_t BUFFER1_STATUS_REGISTER = 0x20000164u;
static const uint32_t BUFFER2_STATUS_REGISTER = 0x20000168u;
static const uint32_t BUFFER_INACTIVE = 0x00000000u;
static const uint32_t BUFFER_ACTIVE = 0x00000001u;
static const uint32_t BUFFER_DATA_READY = 0x00000010u;
static const size_t SRC_LENGTH_MAX = 4096u;
/* erase options */
static const uint32_t ERASE_PARAM_ADDRESS = 0x2000016Cu;
static const uint32_t ERASE_MAIN = 0x00000001u;
static const uint32_t ERASE_INFO = 0x00000002u;
/* Unlock BSL */
static const uint32_t UNLOCK_BSL_ADDRESS = 0x20000170u;
static const uint32_t LOCK_BSL_KEY = 0x00000000u;
static const uint32_t UNLOCK_BSL_KEY = 0x0000000Bu;
/* Address for return code */
static const uint32_t RETURN_CODE_ADDRESS = 0x20000154u;
/* Return codes */
static const uint32_t FLASH_BUSY = 0x00000001u;
static const uint32_t FLASH_SUCCESS = 0x00000ACEu;
static const uint32_t FLASH_ERROR = 0x0000DEADu;
static const uint32_t FLASH_TIMEOUT_ERROR = 0xDEAD0000u;
static const uint32_t FLASH_VERIFY_ERROR = 0xDEADDEADu;
static const uint32_t FLASH_WRONG_COMMAND = 0x00000BADu;
static const uint32_t FLASH_POWER_ERROR = 0x00DEAD00u;
/* Device ID address */
static const uint32_t DEVICE_ID_ADDRESS = 0x0020100Cu;
static const uint32_t PC_REGISTER = 15u;
static const uint32_t SP_REGISTER = 13u;
/* CS silicon and boot code revisions */
static const uint32_t SILICON_REV_ADDRESS = 0x00201010u;
static const uint32_t SILICON_REV_A = 0x00000041u;
static const uint32_t SILICON_REV_B = 0x00000042u;
static const uint32_t SILICON_REV_C = 0x00000043u;
static const uint32_t SILICON_REV_D = 0x00000044u;
static const uint32_t SILICON_REV_E = 0x00000045u;
static const uint32_t SILICON_REV_F = 0x00000046u;
static const uint32_t SILICON_REV_G = 0x00000047u;
static const uint32_t SILICON_REV_H = 0x00000048u;
static const uint32_t SILICON_REV_I = 0x00000049u;
static const uint32_t SILICON_REV_B_WRONG = 0x00004100u;
struct flash_interface {
volatile uint32_t FLASH_FUNCTION;
volatile uint32_t RETURN_CODE;
volatile uint32_t _RESERVED0;
volatile uint32_t DST_ADDRESS;
volatile uint32_t SRC_LENGTH;
volatile uint32_t BUFFER1_STATUS_REGISTER;
volatile uint32_t BUFFER2_STATUS_REGISTER;
volatile uint32_t ERASE_PARAM;
volatile uint32_t UNLOCK_BSL;
};
#define FLASH_LOADER_BASE ((uint32_t)0x20000150u)
#define FLASH_LOADER ((struct flash_interface *) FLASH_LOADER_BASE)
#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P4_FLASHLIBIF_H */

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contrib/loaders/flash/msp432/Makefile Normal file
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BIN2C = ../../../../src/helper/bin2char.sh
CROSS_COMPILE ?= arm-none-eabi-
GCC = $(CROSS_COMPILE)gcc
OBJCOPY = $(CROSS_COMPILE)objcopy
FLAGS = -mcpu=cortex-m4 -march=armv7e-m -mfloat-abi=hard -mfpu=fpv4-sp-d16 -mthumb
CFLAGS = -c -DNO_MSP_CLASSIC_DEFINES -Dgcc -Wall -ffunction-sections
CFLAGS += -fdata-sections -std=c99 -O4
LDFLAGS = -lc -lnosys -Wl,--gc-sections
MSP432E4X_OBJS := \
msp432e4x/driverlib.o \
msp432e4x/main_msp432e4x.o \
msp432e4x/startup_msp432e4.o
MSP432P401X_OBJS := \
msp432p401x/driverlib.o \
msp432p401x/main_msp432p401x.o \
msp432p401x/startup_msp432p4.o
MSP432P411X_OBJS := \
msp432p411x/driverlib.o \
msp432p411x/main_msp432p411x.o \
msp432p411x/startup_msp432p4.o
all: msp432e4x_algo.inc msp432p401x_algo.inc msp432p411x_algo.inc
msp432e4x/%.o: %.c
@echo 'Building file: $<'
@echo 'Invoking: GNU Compiler'
$(GCC) -D__MSP432E4X__ $(FLAGS) $(CFLAGS) -o"$@" "$(shell echo $<)"
@echo 'Finished building: $<'
@echo ' '
msp432p401x/%.o: %.c
@echo 'Building file: $<'
@echo 'Invoking: GNU Compiler'
$(GCC) -D__MSP432P401X__ $(FLAGS) $(CFLAGS) -o"$@" "$(shell echo $<)"
@echo 'Finished building: $<'
@echo ' '
msp432p411x/%.o: %.c
@echo 'Building file: $<'
@echo 'Invoking: GNU Compiler'
$(GCC) -D__MSP432P411X__ $(FLAGS) $(CFLAGS) -o"$@" "$(shell echo $<)"
@echo 'Finished building: $<'
@echo ' '
msp432e4x_algo.out: $(MSP432E4X_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: GNU Linker'
$(GCC) $(FLAGS) $(LDFLAGS) -o$@ $(MSP432E4X_OBJS) -Tmsp432e4x/msp432e4x.lds
@echo 'Finished building target: $@'
@echo ' '
msp432p401x_algo.out: $(MSP432P401X_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: GNU Linker'
$(GCC) $(FLAGS) $(LDFLAGS) -o$@ $(MSP432P401X_OBJS) -Tmsp432p401x/msp432p401x.lds
@echo 'Finished building target: $@'
@echo ' '
msp432p411x_algo.out: $(MSP432P411X_OBJS)
@echo 'Building target: $@'
@echo 'Invoking: GNU Linker'
$(GCC) $(FLAGS) $(LDFLAGS) -o$@ $(MSP432P411X_OBJS) -Tmsp432p411x/msp432p411x.lds
@echo 'Finished building target: $@'
@echo ' '
%.bin: %.out
@echo 'Building target: $@'
@echo 'Invoking: GNU Objcopy Utility'
$(OBJCOPY) -Obinary $< $@
@echo 'Finished building target: $@'
@echo ' '
%.inc: %.bin
@echo 'Building target: $@'
@echo 'Invoking Bin2Char Script'
$(BIN2C) < $< > $@
rm $< $*.out
@echo 'Finished building target: $@'
@echo ' '
clean:
@echo 'Cleaning Targets and Build Artifacts'
rm -rf *.inc *.bin *.out *.map
rm -rf msp432e4x/*.o msp432e4x/*.d
rm -rf msp432p401x/*.o msp432p401x/*.d
rm -rf msp432p411x/*.o msp432p411x/*.d
@echo 'Finished clean'
@echo ' '
.PRECIOUS: %.bin
.PHONY: all clean

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/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "driverlib.h"
/*
* Wrapper function for the CPSID instruction.
* Returns the state of PRIMASK on entry.
*/
uint32_t __attribute__((naked)) cpu_cpsid(void)
{
uint32_t ret;
/* Read PRIMASK and disable interrupts. */
__asm(" mrs r0, PRIMASK\n"
" cpsid i\n"
" bx lr\n"
: "=r" (ret));
/*
* The return is handled in the inline assembly, but the compiler will
* still complain if there is not an explicit return here (despite the fact
* that this does not result in any code being produced because of the
* naked attribute).
*/
return ret;
}
/* Wrapper function for the CPUWFI instruction. */
void __attribute__((naked)) cpu_wfi(void)
{
/* Wait for the next interrupt. */
__asm(" wfi\n"
" bx lr\n");
}
/* Power Control Module APIs */
#if defined(PCM)
static bool __pcm_set_core_voltage_level_advanced(uint_fast8_t voltage_level,
uint32_t time_out, bool blocking)
{
uint8_t power_mode;
uint8_t current_voltage_level;
uint32_t reg_value;
bool bool_timeout;
/* Getting current power mode and level */
power_mode = pcm_get_power_mode();
current_voltage_level = pcm_get_core_voltage_level();
bool_timeout = time_out > 0 ? true : false;
/* If we are already at the power mode they requested, return */
if (current_voltage_level == voltage_level)
return true;
while (current_voltage_level != voltage_level) {
reg_value = PCM->CTL0;
switch (pcm_get_power_state()) {
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
case PCM_AM_LDO_VCORE0:
PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE1)
| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LF_VCORE0:
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LDO_VCORE1:
PCM->CTL0 = (PCM_KEY | (PCM_AM_LDO_VCORE0)
| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
default:
break;
}
if (blocking) {
while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) {
if (bool_timeout && !(--time_out))
return false;
}
} else
return true;
current_voltage_level = pcm_get_core_voltage_level();
}
/* Changing the power mode if we are stuck in LDO mode */
if (power_mode != pcm_get_power_mode()) {
if (power_mode == PCM_DCDC_MODE)
return pcm_set_power_mode(PCM_DCDC_MODE);
else
return pcm_set_power_mode(PCM_LF_MODE);
}
return true;
}
bool pcm_set_core_voltage_level(uint_fast8_t voltage_level)
{
return __pcm_set_core_voltage_level_advanced(voltage_level, 0, true);
}
uint8_t pcm_get_power_mode(void)
{
uint8_t current_power_state;
current_power_state = pcm_get_power_state();
switch (current_power_state) {
case PCM_AM_LDO_VCORE0:
case PCM_AM_LDO_VCORE1:
case PCM_LPM0_LDO_VCORE0:
case PCM_LPM0_LDO_VCORE1:
default:
return PCM_LDO_MODE;
case PCM_AM_DCDC_VCORE0:
case PCM_AM_DCDC_VCORE1:
case PCM_LPM0_DCDC_VCORE0:
case PCM_LPM0_DCDC_VCORE1:
return PCM_DCDC_MODE;
case PCM_LPM0_LF_VCORE0:
case PCM_LPM0_LF_VCORE1:
case PCM_AM_LF_VCORE1:
case PCM_AM_LF_VCORE0:
return PCM_LF_MODE;
}
}
uint8_t pcm_get_core_voltage_level(void)
{
uint8_t current_power_state = pcm_get_power_state();
switch (current_power_state) {
case PCM_AM_LDO_VCORE0:
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LF_VCORE0:
case PCM_LPM0_LDO_VCORE0:
case PCM_LPM0_DCDC_VCORE0:
case PCM_LPM0_LF_VCORE0:
default:
return PCM_VCORE0;
case PCM_AM_LDO_VCORE1:
case PCM_AM_DCDC_VCORE1:
case PCM_AM_LF_VCORE1:
case PCM_LPM0_LDO_VCORE1:
case PCM_LPM0_DCDC_VCORE1:
case PCM_LPM0_LF_VCORE1:
return PCM_VCORE1;
case PCM_LPM3:
return PCM_VCORELPM3;
}
}
static bool __pcm_set_power_mode_advanced(uint_fast8_t power_mode,
uint32_t time_out, bool blocking)
{
uint8_t current_power_mode;
uint8_t current_power_state;
uint32_t reg_value;
bool bool_timeout;
/* Getting Current Power Mode */
current_power_mode = pcm_get_power_mode();
/* If the power mode being set it the same as the current mode, return */
if (power_mode == current_power_mode)
return true;
current_power_state = pcm_get_power_state();
bool_timeout = time_out > 0 ? true : false;
/* Go through the while loop while we haven't achieved the power mode */
while (current_power_mode != power_mode) {
reg_value = PCM->CTL0;
switch (current_power_state) {
case PCM_AM_DCDC_VCORE0:
case PCM_AM_LF_VCORE0:
PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE0
| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LF_VCORE1:
case PCM_AM_DCDC_VCORE1:
PCM->CTL0 = (PCM_KEY | PCM_AM_LDO_VCORE1
| (reg_value & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_AMR_MASK)));
break;
case PCM_AM_LDO_VCORE1: {
if (power_mode == PCM_DCDC_MODE) {
PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE1
| (reg_value & ~(PCM_CTL0_KEY_MASK
| PCM_CTL0_AMR_MASK)));
} else if (power_mode == PCM_LF_MODE) {
PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE1
| (reg_value & ~(PCM_CTL0_KEY_MASK
| PCM_CTL0_AMR_MASK)));
} else
return false;
break;
}
case PCM_AM_LDO_VCORE0: {
if (power_mode == PCM_DCDC_MODE) {
PCM->CTL0 = (PCM_KEY | PCM_AM_DCDC_VCORE0
| (reg_value & ~(PCM_CTL0_KEY_MASK
| PCM_CTL0_AMR_MASK)));
} else if (power_mode == PCM_LF_MODE) {
PCM->CTL0 = (PCM_KEY | PCM_AM_LF_VCORE0
| (reg_value & ~(PCM_CTL0_KEY_MASK
| PCM_CTL0_AMR_MASK)));
} else
return false;
break;
}
default:
break;
}
if (blocking) {
while (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS)) {
if (bool_timeout && !(--time_out))
return false;
}
} else
return true;
current_power_mode = pcm_get_power_mode();
current_power_state = pcm_get_power_state();
}
return true;
}
bool pcm_set_power_mode(uint_fast8_t power_mode)
{
return __pcm_set_power_mode_advanced(power_mode, 0, true);
}
static bool __pcm_set_power_state_advanced(uint_fast8_t power_state,
uint32_t timeout, bool blocking)
{
uint8_t current_power_state;
current_power_state = pcm_get_power_state();
if (current_power_state == power_state)
return true;
switch (power_state) {
case PCM_AM_LDO_VCORE0:
return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
timeout, blocking);
case PCM_AM_LDO_VCORE1:
return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
blocking) && __pcm_set_power_mode_advanced(PCM_LDO_MODE,
timeout, blocking);
case PCM_AM_DCDC_VCORE0:
return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
timeout, blocking);
case PCM_AM_DCDC_VCORE1:
return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
blocking) && __pcm_set_power_mode_advanced(PCM_DCDC_MODE,
timeout, blocking);
case PCM_AM_LF_VCORE0:
return __pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
timeout, blocking);
case PCM_AM_LF_VCORE1:
return __pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
blocking) && __pcm_set_power_mode_advanced(PCM_LF_MODE,
timeout, blocking);
case PCM_LPM0_LDO_VCORE0:
if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
timeout, blocking))
break;
return pcm_goto_lpm0();
case PCM_LPM0_LDO_VCORE1:
if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
blocking) || !__pcm_set_power_mode_advanced(PCM_LDO_MODE,
timeout, blocking))
break;
return pcm_goto_lpm0();
case PCM_LPM0_DCDC_VCORE0:
if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
timeout, blocking))
break;
return pcm_goto_lpm0();
case PCM_LPM0_DCDC_VCORE1:
if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
blocking) || !__pcm_set_power_mode_advanced(PCM_DCDC_MODE,
timeout, blocking))
break;
return pcm_goto_lpm0();
case PCM_LPM0_LF_VCORE0:
if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE0, timeout,
blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
timeout, blocking))
break;
return pcm_goto_lpm0();
case PCM_LPM0_LF_VCORE1:
if (!__pcm_set_core_voltage_level_advanced(PCM_VCORE1, timeout,
blocking) || !__pcm_set_power_mode_advanced(PCM_LF_MODE,
timeout, blocking))
break;
return pcm_goto_lpm0();
case PCM_LPM3:
return pcm_goto_lpm3();
case PCM_LPM4:
return pcm_goto_lpm4();
case PCM_LPM45:
return pcm_shutdown_device(PCM_LPM45);
case PCM_LPM35_VCORE0:
return pcm_shutdown_device(PCM_LPM35_VCORE0);
default:
return false;
}
return false;
}
bool pcm_set_power_state(uint_fast8_t power_state)
{
return __pcm_set_power_state_advanced(power_state, 0, true);
}
bool pcm_shutdown_device(uint32_t shutdown_mode)
{
uint32_t shutdown_mode_bits = (shutdown_mode == PCM_LPM45) ?
PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
/* If a power transition is occuring, return false */
if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
/* Initiating the shutdown */
SCB->SCR |= SCB_SCR_SLEEPDEEP_MSK;
PCM->CTL0 = (PCM_KEY | shutdown_mode_bits
| (PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)));
cpu_wfi();
return true;
}
bool pcm_goto_lpm4(void)
{
/* Disabling RTC_C and WDT_A */
wdt_a_hold_timer();
rtc_c_hold_clock();
/* LPM4 is just LPM3 with WDT_A/RTC_C disabled... */
return pcm_goto_lpm3();
}
bool pcm_goto_lpm0(void)
{
/* If we are in the middle of a state transition, return false */
if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_MSK;
cpu_wfi();
return true;
}
bool pcm_goto_lpm3(void)
{
uint_fast8_t current_power_state;
uint_fast8_t current_power_mode;
/* If we are in the middle of a state transition, return false */
if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
return false;
/* If we are in the middle of a shutdown, return false */
if ((PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_10
|| (PCM->CTL0 & PCM_CTL0_LPMR_MASK) == PCM_CTL0_LPMR_12)
return false;
current_power_mode = pcm_get_power_mode();
current_power_state = pcm_get_power_state();
if (current_power_mode == PCM_DCDC_MODE)
pcm_set_power_mode(PCM_LDO_MODE);
/* Clearing the SDR */
PCM->CTL0 =
(PCM->CTL0 & ~(PCM_CTL0_KEY_MASK | PCM_CTL0_LPMR_MASK)) | PCM_KEY;
/* Setting the sleep deep bit */
SCB->SCR |= SCB_SCR_SLEEPDEEP_MSK;
cpu_wfi();
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_MSK;
return pcm_set_power_state(current_power_state);
}
uint8_t pcm_get_power_state(void)
{
return (PCM->CTL0 & PCM_CTL0_CPM_MASK) >> PCM_CTL0_CPM_OFS;
}
#endif
/* Real Time Clock APIs */
#if defined(RTC_C)
void rtc_c_hold_clock(void)
{
RTC_C->CTL0 = (RTC_C->CTL0 & ~RTC_C_CTL0_KEY_MASK) | RTC_C_KEY;
BITBAND_PERI(RTC_C->CTL13, RTC_C_CTL13_HOLD_OFS) = 1;
BITBAND_PERI(RTC_C->CTL0, RTC_C_CTL0_KEY_OFS) = 0;
}
#endif
/* Watch Dog Timer APIs */
#if defined(WDT_A)
void wdt_a_hold_timer(void)
{
/* Set Hold bit */
uint8_t new_wdt_status = (WDT_A->CTL | WDT_A_CTL_HOLD);
WDT_A->CTL = WDT_A_CTL_PW + new_wdt_status;
}
#endif

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/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H
#define OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H
#include <stdint.h>
#include <stdbool.h>
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__MSP432E4X__)
#include "msp432e4x.h"
#elif defined(__MSP432P401X__)
#include "msp432p401x.h"
#elif defined(__MSP432P411X__)
#include "msp432p411x.h"
#else
#error "Failed to match a device specific include file"
#endif
/* Structure type to access the System Control Block (SCB). */
struct SCB_Type {
volatile uint32_t CPUID; /* CPUID Base Register */
volatile uint32_t ICSR; /* Interrupt Control and State Register */
volatile uint32_t VTOR; /* Vector Table Offset Register */
volatile uint32_t AIRCR; /* Application Interrupt and Reset Control */
volatile uint32_t SCR; /* System Control Register */
volatile uint32_t CCR; /* Configuration Control Register */
volatile uint8_t SHP[12U]; /* System Handlers Priority Registers */
volatile uint32_t SHCSR; /* System Handler Control and State */
volatile uint32_t CFSR; /* Configurable Fault Status Register */
volatile uint32_t HFSR; /* HardFault Status Register */
volatile uint32_t DFSR; /* Debug Fault Status Register */
volatile uint32_t MMFAR; /* MemManage Fault Address Register */
volatile uint32_t BFAR; /* BusFault Address Register */
volatile uint32_t AFSR; /* Auxiliary Fault Status Register */
volatile uint32_t PFR[2U]; /* Processor Feature Register */
volatile uint32_t DFR; /* Debug Feature Register */
volatile uint32_t ADR; /* Auxiliary Feature Register */
volatile uint32_t MMFR[4U]; /* Memory Model Feature Register */
volatile uint32_t ISAR[5U]; /* Instruction Set Attributes Register */
uint32_t RESERVED0[5U];
volatile uint32_t CPACR; /* Coprocessor Access Control Register */
};
/* SCB:SCR register bits */
#define SCB_SCR_SLEEPDEEP_POS 2U
#define SCB_SCR_SLEEPDEEP_MSK (1UL << SCB_SCR_SLEEPDEEP_POS)
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /* System Control Space Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /* System Control Block Base Address */
#define SCB ((struct SCB_Type *)SCB_BASE) /* SCB configuration struct */
/* Definitions of standard bits */
#define BIT0 (uint16_t)(0x0001)
#define BIT1 (uint16_t)(0x0002)
#define BIT2 (uint16_t)(0x0004)
#define BIT3 (uint16_t)(0x0008)
#define BIT4 (uint16_t)(0x0010)
#define BIT5 (uint16_t)(0x0020)
#define BIT6 (uint16_t)(0x0040)
#define BIT7 (uint16_t)(0x0080)
#define BIT8 (uint16_t)(0x0100)
#define BIT9 (uint16_t)(0x0200)
#define BITA (uint16_t)(0x0400)
#define BITB (uint16_t)(0x0800)
#define BITC (uint16_t)(0x1000)
#define BITD (uint16_t)(0x2000)
#define BITE (uint16_t)(0x4000)
#define BITF (uint16_t)(0x8000)
#define BIT(x) ((uint16_t)1 << (x))
/* CPU Module prototypes */
extern uint32_t cpu_cpsid(void);
extern void cpu_wfi(void);
/* Clock Signal Module constants */
#define CS_DCO_FREQUENCY_3 CS_CTL0_DCORSEL_1
#define CS_DCO_FREQUENCY_24 CS_CTL0_DCORSEL_4
/* Power Control Module constants */
#define PCM_KEY 0x695A0000
#define PCM_AM_LDO_VCORE0 0x00
#define PCM_AM_LDO_VCORE1 0x01
#define PCM_AM_DCDC_VCORE0 0x04
#define PCM_AM_DCDC_VCORE1 0x05
#define PCM_AM_LF_VCORE0 0x08
#define PCM_AM_LF_VCORE1 0x09
#define PCM_LPM0_LDO_VCORE0 0x10
#define PCM_LPM0_LDO_VCORE1 0x11
#define PCM_LPM0_DCDC_VCORE0 0x14
#define PCM_LPM0_DCDC_VCORE1 0x15
#define PCM_LPM0_LF_VCORE0 0x18
#define PCM_LPM0_LF_VCORE1 0x19
#define PCM_LPM3 0x20
#define PCM_LPM4 0x21
#define PCM_LPM35_VCORE0 0xC0
#define PCM_LPM45 0xA0
#define PCM_VCORE0 0x00
#define PCM_VCORE1 0x01
#define PCM_VCORELPM3 0x02
#define PCM_LDO_MODE 0x00
#define PCM_DCDC_MODE 0x01
#define PCM_LF_MODE 0x02
/* Power Control Module prototypes */
extern bool pcm_set_core_voltage_level(uint_fast8_t voltage_level);
extern uint8_t pcm_get_core_voltage_level(void);
extern bool pcm_set_power_mode(uint_fast8_t power_mode);
extern uint8_t pcm_get_power_mode(void);
extern bool pcm_set_power_state(uint_fast8_t power_state);
extern uint8_t pcm_get_power_state(void);
extern bool pcm_shutdown_device(uint32_t shutdown_mode);
extern bool pcm_goto_lpm0(void);
extern bool pcm_goto_lpm3(void);
extern bool pcm_goto_lpm4(void);
/* ROM API Function Pointers */
#define ROM_API_TABLE ((unsigned long *)0x02000800)
#define ROM_FLASH_CTL_TABLE ((unsigned long *)(ROM_API_TABLE[7]))
#define ROM_PCM_TABLE ((unsigned long *)(ROM_API_TABLE[13]))
#define ROM_WDT_TABLE ((unsigned long *)(ROM_API_TABLE[25]))
#define ROM_SYS_CTL_A_TABLE ((unsigned long *)(ROM_API_TABLE[26]))
#define ROM_FLASH_CTL_A_TABLE ((unsigned long *)(ROM_API_TABLE[27]))
#if defined(__MSP432P401X__)
#define ROM_FLASH_CTL_UNPROTECT_SECTOR \
((bool (*)(uint_fast8_t memory_space, \
uint32_t sector_mask))ROM_FLASH_CTL_TABLE[4])
#endif
#if defined(__MSP432P401X__)
#define ROM_FLASH_CTL_PROTECT_SECTOR \
((bool (*)(uint_fast8_t memory_space, \
uint32_t sector_mask))ROM_FLASH_CTL_TABLE[5])
#endif
#if defined(__MSP432P401X__)
#define ROM_FLASH_CTL_PERFORM_MASS_ERASE \
((bool (*)(void))ROM_FLASH_CTL_TABLE[8])
#endif
#if defined(__MSP432P401X__)
#define ROM_FLASH_CTL_ERASE_SECTOR \
((bool (*)(uint32_t addr))ROM_FLASH_CTL_TABLE[9])
#endif
#if defined(__MSP432P401X__)
#define ROM_FLASH_CTL_PROGRAM_MEMORY \
((bool (*)(void *src, void *dest, uint32_t length))ROM_FLASH_CTL_TABLE[10])
#endif
#if defined(__MSP432P401X__)
#define ROM_FLASH_CTL_SET_WAIT_STATE \
((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_TABLE[21])
#endif
#if defined(__MSP432P401X__)
#define ROM_FLASH_CTL_GET_WAIT_STATE \
((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_TABLE[22])
#endif
#if defined(__MSP432P401X__)
#define ROM_PCM_SET_CORE_VOLTAGE_LEVEL \
((bool (*)(uint_fast8_t voltage_level))ROM_PCM_TABLE[0])
#endif
#if defined(__MSP432P401X__)
#define ROM_PCM_GET_CORE_VOLTAGE_LEVEL \
((uint8_t (*)(void))ROM_PCM_TABLE[1])
#endif
#if defined(__MSP432P401X__)
#define ROM_PCM_SET_POWER_STATE \
((bool (*)(uint_fast8_t power_state))ROM_PCM_TABLE[6])
#endif
#if defined(__MSP432P401X__)
#define ROM_PCM_GET_POWER_STATE \
((uint8_t (*)(void))ROM_PCM_TABLE[8])
#endif
#if defined(__MSP432P401X__) || defined(__MSP432P411X__)
#define ROM_WDT_A_HOLD_TIMER \
((void (*)(void))ROM_WDT_TABLE[0])
#endif
#if defined(__MSP432P411X__)
#define ROM_SYS_CTL_A_GET_FLASH_SIZE \
((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[1])
#endif
#if defined(__MSP432P411X__)
#define ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE \
((uint_least32_t (*)(void))ROM_SYS_CTL_A_TABLE[18])
#endif
#if defined(__MSP432P411X__)
#define ROM_FLASH_CTL_A_UNPROTECT_MEMORY \
((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[4])
#endif
#if defined(__MSP432P411X__)
#define ROM_FLASH_CTL_A_PROTECT_MEMORY \
((bool (*)(uint32_t start_addr, uint32_t end_addr))ROM_FLASH_CTL_A_TABLE[5])
#endif
#if defined(__MSP432P411X__)
#define ROM_FLASH_CTL_A_PERFORM_MASS_ERASE \
((bool (*)(void))ROM_FLASH_CTL_A_TABLE[8])
#endif
#if defined(__MSP432P411X__)
#define ROM_FLASH_CTL_A_ERASE_SECTOR \
((bool (*)(uint32_t addr))ROM_FLASH_CTL_A_TABLE[9])
#endif
#if defined(__MSP432P411X__)
#define ROM_FLASH_CTL_A_PROGRAM_MEMORY \
((bool (*)(void *src, void *dest, uint32_t length)) \
ROM_FLASH_CTL_A_TABLE[10])
#endif
#if defined(__MSP432P411X__)
#define ROM_FLASH_CTL_A_SET_WAIT_STATE \
((void (*)(uint32_t bank, uint32_t wait_state))ROM_FLASH_CTL_A_TABLE[21])
#endif
#if defined(__MSP432P411X__)
#define ROM_FLASH_CTL_A_GET_WAIT_STATE \
((uint32_t (*)(uint32_t bank))ROM_FLASH_CTL_A_TABLE[22])
#endif
/* Map API functions to ROM or locally built functions */
#ifdef ROM_FLASH_CTL_UNPROTECT_SECTOR
#define MAP_FLASH_CTL_UNPROTECT_SECTOR ROM_FLASH_CTL_UNPROTECT_SECTOR
#else
#define MAP_FLASH_CTL_UNPROTECT_SECTOR flash_ctl_unprotect_sector
#endif
#ifdef ROM_FLASH_CTL_PROTECT_SECTOR
#define MAP_FLASH_CTL_PROTECT_SECTOR ROM_FLASH_CTL_PROTECT_SECTOR
#else
#define MAP_FLASH_CTL_PROTECT_SECTOR flash_ctl_protect_sector
#endif
#ifdef ROM_FLASH_CTL_PERFORM_MASS_ERASE
#define MAP_FLASH_CTL_PERFORM_MASS_ERASE ROM_FLASH_CTL_PERFORM_MASS_ERASE
#else
#define MAP_FLASH_CTL_PERFORM_MASS_ERASE flash_ctl_perform_mass_erase
#endif
#ifdef ROM_FLASH_CTL_ERASE_SECTOR
#define MAP_FLASH_CTL_ERASE_SECTOR ROM_FLASH_CTL_ERASE_SECTOR
#else
#define MAP_FLASH_CTL_ERASE_SECTOR flash_ctl_erase_sector
#endif
#ifdef ROM_FLASH_CTL_PROGRAM_MEMORY
#define MAP_FLASH_CTL_PROGRAM_MEMORY ROM_FLASH_CTL_PROGRAM_MEMORY
#else
#define MAP_FLASH_CTL_PROGRAM_MEMORY flash_ctl_program_memory
#endif
#ifdef ROM_FLASH_CTL_SET_WAIT_STATE
#define MAP_FLASH_CTL_SET_WAIT_STATE ROM_FLASH_CTL_SET_WAIT_STATE
#else
#define MAP_FLASH_CTL_SET_WAIT_STATE flash_ctl_set_wait_state
#endif
#ifdef ROM_FLASH_CTL_GET_WAIT_STATE
#define MAP_FLASH_CTL_GET_WAIT_STATE ROM_FLASH_CTL_GET_WAIT_STATE
#else
#define MAP_FLASH_CTL_GET_WAIT_STATE flash_ctl_get_wait_state
#endif
#ifdef ROM_PCM_SET_CORE_VOLTAGE_LEVEL
#define MAP_PCM_SET_CORE_VOLTAGE_LEVEL ROM_PCM_SET_CORE_VOLTAGE_LEVEL
#else
#define MAP_PCM_SET_CORE_VOLTAGE_LEVEL pcm_set_core_voltage_level
#endif
#ifdef ROM_PCM_GET_CORE_VOLTAGE_LEVEL
#define MAP_PCM_GET_CORE_VOLTAGE_LEVEL ROM_PCM_GET_CORE_VOLTAGE_LEVEL
#else
#define MAP_PCM_GET_CORE_VOLTAGE_LEVEL pcm_get_core_voltage_level
#endif
#ifdef ROM_PCM_SET_POWER_STATE
#define MAP_PCM_SET_POWER_STATE ROM_PCM_SET_POWER_STATE
#else
#define MAP_PCM_SET_POWER_STATE pcm_set_power_state
#endif
#ifdef ROM_PCM_GET_POWER_STATE
#define MAP_PCM_GET_POWER_STATE ROM_PCM_GET_POWER_STATE
#else
#define MAP_PCM_GET_POWER_STATE pcm_get_power_state
#endif
#ifdef ROM_WDT_A_HOLD_TIMER
#define MAP_WDT_A_HOLD_TIMER ROM_WDT_A_HOLD_TIMER
#else
#define MAP_WDT_A_HOLD_TIMER wdt_a_hold_timer
#endif
#ifdef ROM_SYS_CTL_A_GET_FLASH_SIZE
#define MAP_SYS_CTL_A_GET_FLASH_SIZE ROM_SYS_CTL_A_GET_FLASH_SIZE
#else
#define MAP_SYS_CTL_A_GET_FLASH_SIZE sys_ctl_a_get_flash_size
#endif
#ifdef ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE
#define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE ROM_SYS_CTL_A_GET_INFO_FLASH_SIZE
#else
#define MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE sys_ctl_a_get_info_flash_size
#endif
#ifdef ROM_FLASH_CTL_A_UNPROTECT_MEMORY
#define MAP_FLASH_CTL_A_UNPROTECT_MEMORY ROM_FLASH_CTL_A_UNPROTECT_MEMORY
#else
#define MAP_FLASH_CTL_A_UNPROTECT_MEMORY flash_ctl_a_unprotect_memory
#endif
#ifdef ROM_FLASH_CTL_A_PROTECT_MEMORY
#define MAP_FLASH_CTL_A_PROTECT_MEMORY ROM_FLASH_CTL_A_PROTECT_MEMORY
#else
#define MAP_FLASH_CTL_A_PROTECT_MEMORY flash_ctl_a_protect_memory
#endif
#ifdef ROM_FLASH_CTL_A_PERFORM_MASS_ERASE
#define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE ROM_FLASH_CTL_A_PERFORM_MASS_ERASE
#else
#define MAP_FLASH_CTL_A_PERFORM_MASS_ERASE flash_ctl_a_perform_mass_erase
#endif
#ifdef ROM_FLASH_CTL_A_ERASE_SECTOR
#define MAP_FLASH_CTL_A_ERASE_SECTOR ROM_FLASH_CTL_A_ERASE_SECTOR
#else
#define MAP_FLASH_CTL_A_ERASE_SECTOR flash_ctl_a_erase_sector
#endif
#ifdef ROM_FLASH_CTL_A_PROGRAM_MEMORY
#define MAP_FLASH_CTL_A_PROGRAM_MEMORY ROM_FLASH_CTL_A_PROGRAM_MEMORY
#else
#define MAP_FLASH_CTL_A_PROGRAM_MEMORY flash_ctl_a_program_memory
#endif
#ifdef ROM_FLASH_CTL_A_SET_WAIT_STATE
#define MAP_FLASH_CTL_A_SET_WAIT_STATE ROM_FLASH_CTL_A_SET_WAIT_STATE
#else
#define MAP_FLASH_CTL_A_SET_WAIT_STATE flash_ctl_a_set_wait_state
#endif
#ifdef ROM_FLASH_CTL_A_GET_WAIT_STATE
#define MAP_FLASH_CTL_A_GET_WAIT_STATE ROM_FLASH_CTL_A_GET_WAIT_STATE
#else
#define MAP_FLASH_CTL_A_GET_WAIT_STATE flash_ctl_a_get_wait_state
#endif
/* Real Time Clock Module prototypes */
extern void rtc_c_hold_clock(void);
/* Watchdog Timer Module prototypes */
extern void wdt_a_hold_timer(void);
#if defined(__MCU_HAS_FLCTL_A__)
#define FLASH_A_BANK0 0x00
#define FLASH_A_BANK1 0x01
#define __INFO_FLASH_A_TECH_START__ 0x00200000
#define __INFO_FLASH_A_TECH_MIDDLE__ 0x00204000
#endif
#if defined(__MCU_HAS_FLCTL__)
#define FLASH_BANK0 0x00
#define FLASH_BANK1 0x01
#define FLASH_MAIN_MEMORY_SPACE_BANK0 0x01
#define FLASH_MAIN_MEMORY_SPACE_BANK1 0x02
#define FLASH_INFO_MEMORY_SPACE_BANK0 0x03
#define FLASH_INFO_MEMORY_SPACE_BANK1 0x04
#define FLASH_SECTOR0 FLCTL_BANK0_MAIN_WEPROT_PROT0
#define FLASH_SECTOR1 FLCTL_BANK0_MAIN_WEPROT_PROT1
#endif
#ifdef __cplusplus
}
#endif
#endif /* OPENOCD_LOADERS_FLASH_MSP432_DRIVERLIB_H */

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/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "driverlib.h"
#include "MSP432E4_FlashLibIf.h"
/* Local prototypes */
void msp432_flash_init(void);
void msp432_flash_mass_erase(void);
void msp432_flash_sector_erase(void);
void msp432_flash_write(void);
void msp432_flash_continous_write(void);
void msp432_flash_exit(void);
int main(void)
{
/* Disable interrupts */
__asm(" cpsid i");
/* Halt watchdog */
SYSCTL->RCGCWD &= ~(SYSCTL_RCGCWD_R1 + SYSCTL_RCGCWD_R0);
while (1) {
switch (FLASH_LOADER->FLASH_FUNCTION) {
case FLASH_INIT:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_init();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_MASS_ERASE:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_mass_erase();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_SECTOR_ERASE:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_sector_erase();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_PROGRAM:
case FLASH_CONTINUOUS_PROGRAM:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_continous_write();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_EXIT:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_exit();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_NO_COMMAND:
break;
default:
FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
break;
}
}
}
/* Initialize flash */
void msp432_flash_init(void)
{
SCB->VTOR = 0x20000000;
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Erase entire flash */
void msp432_flash_mass_erase(void)
{
bool success = false;
/* Clear the flash access and error interrupts. */
FLASH_CTRL->FCMISC = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_ERMISC | FLASH_FCMISC_PMISC);
/* Trigger mass erase */
FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_MERASE;
while (FLASH_CTRL->FMC & FLASH_FMC_MERASE)
;
/* Return an error if an access violation occurred. */
success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_ERRIS));
if (!success)
FLASH_LOADER->RETURN_CODE = FLASH_VERIFY_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Erase one flash sector */
void msp432_flash_sector_erase(void)
{
bool success = false;
/* Clear the flash access and error interrupts. */
FLASH_CTRL->FCMISC = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_ERMISC | FLASH_FCMISC_PMISC);
/* Set 16kB aligned flash page address to be erased (16kB block) */
FLASH_CTRL->FMA = FLASH_LOADER->DST_ADDRESS;
/* Trigger sector erase (erase flash page) */
FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_ERASE;
while (FLASH_CTRL->FMC & FLASH_FMC_ERASE)
;
/* Return an error if an access violation occurred. */
success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_ERRIS));
if (!success)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Write data to flash */
void msp432_flash_continous_write(void)
{
bool buffer1_in_use = false;
bool buffer2_in_use = false;
uint32_t *src_address = NULL;
bool success = true;
uint32_t i = 0;
uint32_t address = FLASH_LOADER->DST_ADDRESS;
uint32_t data_to_write = FLASH_LOADER->SRC_LENGTH;
int32_t write_package = 0;
/* Clear the flash access and error interrupts. */
FLASH_CTRL->FCMISC = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC | FLASH_FCMISC_PMISC);
do {
if (data_to_write > SRC_LENGTH_MAX) {
write_package = SRC_LENGTH_MAX;
data_to_write -= write_package;
} else {
write_package = data_to_write;
data_to_write -= write_package;
}
while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) &&
!(FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY))
;
if (FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) {
FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE;
src_address = (uint32_t *) RAM_LOADER_BUFFER1;
buffer1_in_use = true;
} else if (FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY) {
FLASH_LOADER->BUFFER2_STATUS_REGISTER |= BUFFER_ACTIVE;
src_address = (uint32_t *) RAM_LOADER_BUFFER2;
buffer2_in_use = true;
}
/*
* The flash hardware can only write complete words to flash. If
* an unaligned address is passed in, we must do a read-modify-write
* on a word with enough bytes to align the rest of the buffer. And
* if less than a whole word remains at the end, we must also do a
* read-modify-write on a final word to finish up.
*/
if (0 != (address & 0x3)) {
uint32_t head;
uint8_t *ui8head = (uint8_t *)&head;
uint8_t *buffer = (uint8_t *)src_address;
/* Get starting offset for data to write (will be 1 to 3) */
uint32_t head_offset = address & 0x03;
/* Get the aligned address to write this first word to */
uint32_t head_address = address & 0xfffffffc;
/* Retrieve what is already in flash at the head address */
head = *(uint32_t *)head_address;
/* Substitute in the new data to write */
while ((write_package > 0) && (head_offset < 4)) {
ui8head[head_offset] = *buffer;
head_offset++;
address++;
buffer++;
write_package--;
}
src_address = (uint32_t *)buffer;
FLASH_CTRL->FMD = head;
FLASH_CTRL->FMA = head_address;
FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
/* Wait until the word has been programmed. */
while (FLASH_CTRL->FMC & FLASH_FMC_WRITE)
;
/* Return an error if an access violation occurred. */
success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS |
FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS));
}
/* Program a word at a time until aligned on 32-word boundary */
while ((write_package >= 4) && ((address & 0x7f) != 0) && success) {
FLASH_CTRL->FMD = *src_address++;
FLASH_CTRL->FMA = address;
FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
/* Wait until the word has been programmed. */
while (FLASH_CTRL->FMC & FLASH_FMC_WRITE)
;
/* Prepare for next word to write */
write_package -= 4;
address += 4;
/* Return an error if an access violation occurred. */
success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS |
FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS));
}
/* Program data in 32-word blocks */
while ((write_package >= 32) && success) {
/* Loop over the words in this 32-word block. */
i = 0;
do {
FLASH_CTRL->FWBN[i] = *src_address++;
write_package -= 4;
i++;
} while ((write_package > 0) && (i < 32));
FLASH_CTRL->FMA = address;
FLASH_CTRL->FMC2 = FLASH_FMC_WRKEY | FLASH_FMC2_WRBUF;
/* Wait until the write buffer has been programmed. */
while (FLASH_CTRL->FMC2 & FLASH_FMC2_WRBUF)
;
/* Increment destination address by words written */
address += 128;
/* Return an error if an access violation occurred. */
success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS |
FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS));
}
/* Program a word at a time on left over data */
while ((write_package >= 4) && success) {
FLASH_CTRL->FMD = *src_address++;
FLASH_CTRL->FMA = address;
FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
/* Wait until the word has been programmed. */
while (FLASH_CTRL->FMC & FLASH_FMC_WRITE)
;
/* Prepare for next word to write */
write_package -= 4;
address += 4;
/* Return an error if an access violation occurred. */
success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS |
FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS));
}
if ((write_package > 0) && success) {
uint32_t tail;
uint8_t *ui8tail = (uint8_t *)&tail;
uint8_t *buffer = (uint8_t *)src_address;
/* Set starting offset for data to write */
uint32_t tail_offset = 0;
/* Get the address to write this last word to */
uint32_t tail_address = address;
/* Retrieve what is already in flash at the tail address */
tail = *(uint32_t *)address;
/* Substitute in the new data to write */
while (write_package > 0) {
ui8tail[tail_offset] = *buffer;
tail_offset++;
address++;
buffer++;
write_package--;
}
FLASH_CTRL->FMD = tail;
FLASH_CTRL->FMA = tail_address;
FLASH_CTRL->FMC = FLASH_FMC_WRKEY | FLASH_FMC_WRITE;
/* Wait until the word has been programmed. */
while (FLASH_CTRL->FMC & FLASH_FMC_WRITE)
;
/* Return an error if an access violation occurred. */
success = !(FLASH_CTRL->FCRIS & (FLASH_FCRIS_ARIS |
FLASH_FCRIS_ERIS | FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS));
}
if (buffer1_in_use) {
FLASH_LOADER->BUFFER1_STATUS_REGISTER &=
~(BUFFER_ACTIVE | BUFFER_DATA_READY);
buffer1_in_use = false;
} else if (buffer2_in_use) {
FLASH_LOADER->BUFFER2_STATUS_REGISTER &=
~(BUFFER_ACTIVE | BUFFER_DATA_READY);
buffer2_in_use = false;
}
} while (success && data_to_write);
if (!success)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Exit flash programming */
void msp432_flash_exit(void)
{
SCB->VTOR = 0x00000000;
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}

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/******************************************************************************
*
* Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "driverlib.h"
#include "MSP432P4_FlashLibIf.h"
/* Number of erase repeats until timeout */
#define FLASH_MAX_REPEATS 5
/* Local prototypes */
void msp432_flash_init(void);
void msp432_flash_mass_erase(void);
void msp432_flash_sector_erase(void);
void msp432_flash_write(void);
void msp432_flash_continous_write(void);
void msp432_flash_exit(void);
void unlock_flash_sectors(void);
void unlock_all_flash_sectors(void);
void lock_all_flash_sectors(void);
void __cs_set_dco_frequency_range(uint32_t dco_freq);
static bool program_device(void *src, void *dest, uint32_t length);
struct backup_params {
uint32_t BANK0_WAIT_RESTORE;
uint32_t BANK1_WAIT_RESTORE;
uint32_t CS_DC0_FREQ_RESTORE;
uint8_t VCORE_LEVEL_RESTORE;
uint8_t PCM_VCORE_LEVEL_RESTORE;
};
#define BACKUP_PARAMS ((struct backup_params *) 0x20000180)
/* Main with trampoline */
int main(void)
{
/* Halt watchdog */
MAP_WDT_A_HOLD_TIMER();
/* Disable interrupts */
cpu_cpsid();
while (1) {
switch (FLASH_LOADER->FLASH_FUNCTION) {
case FLASH_INIT:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_init();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_MASS_ERASE:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_mass_erase();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_SECTOR_ERASE:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_sector_erase();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_PROGRAM:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_write();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_CONTINUOUS_PROGRAM:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_continous_write();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_EXIT:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_exit();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_NO_COMMAND:
break;
default:
FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
break;
}
}
}
/* Initialize flash */
void msp432_flash_init(void)
{
bool success = false;
/* Point to vector table in RAM */
SCB->VTOR = (uint32_t)0x01000000;
/* backup system parameters */
BACKUP_PARAMS->BANK0_WAIT_RESTORE =
MAP_FLASH_CTL_GET_WAIT_STATE(FLASH_BANK0);
BACKUP_PARAMS->BANK1_WAIT_RESTORE =
MAP_FLASH_CTL_GET_WAIT_STATE(FLASH_BANK1);
BACKUP_PARAMS->VCORE_LEVEL_RESTORE = MAP_PCM_GET_CORE_VOLTAGE_LEVEL();
BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE = MAP_PCM_GET_POWER_STATE();
BACKUP_PARAMS->CS_DC0_FREQ_RESTORE = CS->CTL0 & CS_CTL0_DCORSEL_MASK;
/* set parameters for flashing */
success = MAP_PCM_SET_POWER_STATE(PCM_AM_LDO_VCORE0);
/* Set Flash wait states to 2 */
MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK0, 2);
MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK1, 2);
/* Set CPU speed to 24MHz */
__cs_set_dco_frequency_range(CS_DCO_FREQUENCY_24);
if (!success) {
/* Indicate failed power switch */
FLASH_LOADER->RETURN_CODE = FLASH_POWER_ERROR;
} else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Erase entire flash */
void msp432_flash_mass_erase(void)
{
bool success = false;
/* Allow flash writes */
unlock_flash_sectors();
/* Allow some mass erase repeats before timeout with error */
int erase_repeats = FLASH_MAX_REPEATS;
while (!success && (erase_repeats > 0)) {
/* Mass erase with post-verify */
success = MAP_FLASH_CTL_PERFORM_MASS_ERASE();
erase_repeats--;
}
if (erase_repeats == 0)
FLASH_LOADER->RETURN_CODE = FLASH_VERIFY_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
/* Block flash writes */
lock_all_flash_sectors();
}
/* Erase one flash sector */
void msp432_flash_sector_erase(void)
{
bool success = false;
/* Allow flash writes */
unlock_all_flash_sectors();
/* Allow some sector erase repeats before timeout with error */
int erase_repeats = FLASH_MAX_REPEATS;
while (!success && (erase_repeats > 0)) {
/* Sector erase with post-verify */
success = MAP_FLASH_CTL_ERASE_SECTOR(FLASH_LOADER->DST_ADDRESS);
erase_repeats--;
}
if (erase_repeats == 0)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
/* Block flash writes */
lock_all_flash_sectors();
}
/* Write data to flash with the help of DriverLib */
void msp432_flash_write(void)
{
bool success = false;
/* Allow flash writes */
unlock_all_flash_sectors();
while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY))
;
FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE;
/* Program memory */
success = program_device((uint32_t *)RAM_LOADER_BUFFER1,
(void *)FLASH_LOADER->DST_ADDRESS, FLASH_LOADER->SRC_LENGTH);
FLASH_LOADER->BUFFER1_STATUS_REGISTER &=
~(BUFFER_ACTIVE | BUFFER_DATA_READY);
/* Block flash writes */
lock_all_flash_sectors();
if (!success)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Write data to flash with the help of DriverLib with auto-increment */
void msp432_flash_continous_write(void)
{
bool buffer1_in_use = false;
bool buffer2_in_use = false;
uint32_t *src_address = NULL;
bool success = false;
uint32_t bytes_to_write = FLASH_LOADER->SRC_LENGTH;
uint32_t write_package = 0;
uint32_t start_addr = FLASH_LOADER->DST_ADDRESS;
while (bytes_to_write > 0) {
if (bytes_to_write > SRC_LENGTH_MAX) {
write_package = SRC_LENGTH_MAX;
bytes_to_write -= write_package;
} else {
write_package = bytes_to_write;
bytes_to_write -= write_package;
}
unlock_all_flash_sectors();
while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) &&
!(FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY))
;
if (FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) {
FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE;
src_address = (uint32_t *)RAM_LOADER_BUFFER1;
buffer1_in_use = true;
} else if (FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY) {
FLASH_LOADER->BUFFER2_STATUS_REGISTER |= BUFFER_ACTIVE;
src_address = (uint32_t *)RAM_LOADER_BUFFER2;
buffer2_in_use = true;
}
if (buffer1_in_use || buffer2_in_use) {
success = program_device(src_address,
(void *)start_addr, write_package);
if (buffer1_in_use)
P6->OUT &= ~BIT4; /* Program from B1 */
else if (buffer2_in_use)
P3->OUT &= ~BIT6; /* Program from B1 */
start_addr += write_package;
}
if (buffer1_in_use) {
FLASH_LOADER->BUFFER1_STATUS_REGISTER &=
~(BUFFER_ACTIVE | BUFFER_DATA_READY);
buffer1_in_use = false;
} else if (buffer2_in_use) {
FLASH_LOADER->BUFFER2_STATUS_REGISTER &=
~(BUFFER_ACTIVE | BUFFER_DATA_READY);
buffer2_in_use = false;
}
/* Block flash writes */
lock_all_flash_sectors();
if (!success) {
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
break;
}
}
if (success)
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Unlock Main/Info Flash sectors */
void unlock_flash_sectors(void)
{
if (FLASH_LOADER->ERASE_PARAM & ERASE_MAIN) {
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK0,
0xFFFFFFFF);
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK1,
0xFFFFFFFF);
}
if (FLASH_LOADER->ERASE_PARAM & ERASE_INFO) {
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK0,
FLASH_SECTOR0 | FLASH_SECTOR1);
if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY)
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK1,
FLASH_SECTOR0 | FLASH_SECTOR1);
}
}
/* Unlock All Flash sectors */
void unlock_all_flash_sectors(void)
{
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK0, 0xFFFFFFFF);
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK1, 0xFFFFFFFF);
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK0,
FLASH_SECTOR0 | FLASH_SECTOR1);
if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY)
MAP_FLASH_CTL_UNPROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK1,
FLASH_SECTOR0 | FLASH_SECTOR1);
}
/* Lock all Flash sectors */
void lock_all_flash_sectors(void)
{
MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK0, 0xFFFFFFFF);
MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_MAIN_MEMORY_SPACE_BANK1, 0xFFFFFFFF);
MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK0,
FLASH_SECTOR0 | FLASH_SECTOR1);
MAP_FLASH_CTL_PROTECT_SECTOR(FLASH_INFO_MEMORY_SPACE_BANK1,
FLASH_SECTOR0 | FLASH_SECTOR1);
}
/* Force DCO frequency range */
void __cs_set_dco_frequency_range(uint32_t dco_freq)
{
/* Unlocking the CS Module */
CS->KEY = CS_KEY_VAL;
/* Resetting Tuning Parameters and Setting the frequency */
CS->CTL0 = (CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dco_freq;
/* Locking the CS Module */
CS->KEY = 0;
}
/* Exit flash programming */
void msp432_flash_exit(void)
{
bool success = false;
/* Restore modified registers, in reverse order */
__cs_set_dco_frequency_range(CS_DCO_FREQUENCY_3);
MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK0,
BACKUP_PARAMS->BANK0_WAIT_RESTORE);
MAP_FLASH_CTL_SET_WAIT_STATE(FLASH_BANK1,
BACKUP_PARAMS->BANK1_WAIT_RESTORE);
success = MAP_PCM_SET_POWER_STATE(BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE);
success &= MAP_PCM_SET_CORE_VOLTAGE_LEVEL(
BACKUP_PARAMS->VCORE_LEVEL_RESTORE);
__cs_set_dco_frequency_range(BACKUP_PARAMS->CS_DC0_FREQ_RESTORE);
/* Point to vector table in Flash */
SCB->VTOR = (uint32_t)0x00000000;
if (!success)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
static bool program_device(void *src, void *dest, uint32_t length)
{
return MAP_FLASH_CTL_PROGRAM_MEMORY(src, dest, length);
}

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/******************************************************************************
*
* Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
#include <stdbool.h>
#include "driverlib.h"
#include "MSP432P4_FlashLibIf.h"
/* Number of erase repeats until timeout */
#define FLASH_MAX_REPEATS 5
/* Local prototypes */
void msp432_flash_init(void);
void msp432_flash_mass_erase(void);
void msp432_flash_sector_erase(void);
void msp432_flash_write(void);
void msp432_flash_continous_write(void);
void msp432_flash_exit(void);
void unlock_flash_sectors(void);
void unlock_all_flash_sectors(void);
void lock_all_flash_sectors(void);
void __cs_set_dco_frequency_range(uint32_t dco_freq);
static bool program_device(void *src, void *dest, uint32_t length);
struct backup_params {
uint32_t BANK0_WAIT_RESTORE;
uint32_t BANK1_WAIT_RESTORE;
uint32_t CS_DC0_FREQ_RESTORE;
uint8_t VCORE_LEVEL_RESTORE;
uint8_t PCM_VCORE_LEVEL_RESTORE;
};
#define BACKUP_PARAMS ((struct backup_params *) 0x20000180)
#define INFO_FLASH_START __INFO_FLASH_A_TECH_START__
#define INFO_FLASH_MIDDLE __INFO_FLASH_A_TECH_MIDDLE__
#define BSL_FLASH_START BSL_API_TABLE_ADDR
/* Main with trampoline */
int main(void)
{
/* Halt watchdog */
MAP_WDT_A_HOLD_TIMER();
/* Disable interrupts */
cpu_cpsid();
while (1) {
switch (FLASH_LOADER->FLASH_FUNCTION) {
case FLASH_INIT:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_init();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_MASS_ERASE:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_mass_erase();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_SECTOR_ERASE:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_sector_erase();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_PROGRAM:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_write();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_CONTINUOUS_PROGRAM:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_continous_write();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_EXIT:
FLASH_LOADER->RETURN_CODE = FLASH_BUSY;
msp432_flash_exit();
FLASH_LOADER->FLASH_FUNCTION = 0;
break;
case FLASH_NO_COMMAND:
break;
default:
FLASH_LOADER->RETURN_CODE = FLASH_WRONG_COMMAND;
break;
}
}
}
/* Initialize flash */
void msp432_flash_init(void)
{
bool success = false;
/* Point to vector table in RAM */
SCB->VTOR = (uint32_t)0x01000000;
/* backup system parameters */
BACKUP_PARAMS->BANK0_WAIT_RESTORE =
MAP_FLASH_CTL_A_GET_WAIT_STATE(FLASH_A_BANK0);
BACKUP_PARAMS->BANK1_WAIT_RESTORE =
MAP_FLASH_CTL_A_GET_WAIT_STATE(FLASH_A_BANK1);
BACKUP_PARAMS->VCORE_LEVEL_RESTORE = MAP_PCM_GET_CORE_VOLTAGE_LEVEL();
BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE = MAP_PCM_GET_POWER_STATE();
BACKUP_PARAMS->CS_DC0_FREQ_RESTORE = CS->CTL0 & CS_CTL0_DCORSEL_MASK;
/* set parameters for flashing */
success = MAP_PCM_SET_POWER_STATE(PCM_AM_LDO_VCORE0);
/* Set Flash wait states to 2 */
MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK0, 2);
MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK1, 2);
/* Set CPU speed to 24MHz */
__cs_set_dco_frequency_range(CS_DCO_FREQUENCY_24);
if (!success) {
/* Indicate failed power switch */
FLASH_LOADER->RETURN_CODE = FLASH_POWER_ERROR;
} else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Erase entire flash */
void msp432_flash_mass_erase(void)
{
bool success = false;
/* Allow flash writes */
unlock_flash_sectors();
/* Allow some mass erase repeats before timeout with error */
int erase_repeats = FLASH_MAX_REPEATS;
while (!success && (erase_repeats > 0)) {
/* Mass erase with post-verify */
success = ROM_FLASH_CTL_A_PERFORM_MASS_ERASE();
erase_repeats--;
}
if (erase_repeats == 0)
FLASH_LOADER->RETURN_CODE = FLASH_VERIFY_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
/* Block flash writes */
lock_all_flash_sectors();
}
/* Erase one flash sector */
void msp432_flash_sector_erase(void)
{
bool success = false;
/* Allow flash writes */
unlock_all_flash_sectors();
/* Allow some sector erase repeats before timeout with error */
int erase_repeats = FLASH_MAX_REPEATS;
while (!success && (erase_repeats > 0)) {
/* Sector erase with post-verify */
success = MAP_FLASH_CTL_A_ERASE_SECTOR(FLASH_LOADER->DST_ADDRESS);
erase_repeats--;
}
if (erase_repeats == 0)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
/* Block flash writes */
lock_all_flash_sectors();
}
/* Write data to flash with the help of DriverLib */
void msp432_flash_write(void)
{
bool success = false;
/* Allow flash writes */
unlock_all_flash_sectors();
while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY))
;
FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE;
/* Program memory */
success = program_device((uint32_t *)RAM_LOADER_BUFFER1,
(void *)FLASH_LOADER->DST_ADDRESS, FLASH_LOADER->SRC_LENGTH);
FLASH_LOADER->BUFFER1_STATUS_REGISTER &=
~(BUFFER_ACTIVE | BUFFER_DATA_READY);
/* Block flash writes */
lock_all_flash_sectors();
if (!success)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Write data to flash with the help of DriverLib with auto-increment */
void msp432_flash_continous_write(void)
{
bool buffer1_in_use = false;
bool buffer2_in_use = false;
uint32_t *src_address = NULL;
bool success = false;
uint32_t bytes_to_write = FLASH_LOADER->SRC_LENGTH;
uint32_t write_package = 0;
uint32_t start_addr = FLASH_LOADER->DST_ADDRESS;
while (bytes_to_write > 0) {
if (bytes_to_write > SRC_LENGTH_MAX) {
write_package = SRC_LENGTH_MAX;
bytes_to_write -= write_package;
} else {
write_package = bytes_to_write;
bytes_to_write -= write_package;
}
unlock_all_flash_sectors();
while (!(FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) &&
!(FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY))
;
if (FLASH_LOADER->BUFFER1_STATUS_REGISTER & BUFFER_DATA_READY) {
FLASH_LOADER->BUFFER1_STATUS_REGISTER |= BUFFER_ACTIVE;
src_address = (uint32_t *) RAM_LOADER_BUFFER1;
buffer1_in_use = true;
} else if (FLASH_LOADER->BUFFER2_STATUS_REGISTER & BUFFER_DATA_READY) {
FLASH_LOADER->BUFFER2_STATUS_REGISTER |= BUFFER_ACTIVE;
src_address = (uint32_t *) RAM_LOADER_BUFFER2;
buffer2_in_use = true;
}
if (buffer1_in_use || buffer2_in_use) {
success = program_device(src_address, (void *) start_addr, write_package);
start_addr += write_package;
}
if (buffer1_in_use) {
FLASH_LOADER->BUFFER1_STATUS_REGISTER &= ~(BUFFER_ACTIVE | BUFFER_DATA_READY);
buffer1_in_use = false;
} else if (buffer2_in_use) {
FLASH_LOADER->BUFFER2_STATUS_REGISTER &= ~(BUFFER_ACTIVE | BUFFER_DATA_READY);
buffer2_in_use = false;
}
/* Block flash writes */
lock_all_flash_sectors();
if (!success) {
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
break;
}
}
if (success)
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
/* Unlock Main/Info Flash sectors */
void unlock_flash_sectors(void)
{
if (FLASH_LOADER->ERASE_PARAM & ERASE_MAIN)
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(FLASH_BASE, FLASH_BASE +
MAP_SYS_CTL_A_GET_FLASH_SIZE() - 1);
if (FLASH_LOADER->ERASE_PARAM & ERASE_INFO) {
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_START, TLV_BASE - 1);
if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY)
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(BSL_FLASH_START,
INFO_FLASH_MIDDLE - 1);
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_MIDDLE, INFO_FLASH_MIDDLE +
MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE() - 1);
}
}
/* Unlock All Flash sectors */
void unlock_all_flash_sectors(void)
{
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(FLASH_BASE, FLASH_BASE +
MAP_SYS_CTL_A_GET_FLASH_SIZE() - 1);
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_START, TLV_BASE - 1);
if (FLASH_LOADER->UNLOCK_BSL == UNLOCK_BSL_KEY)
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(BSL_FLASH_START,
INFO_FLASH_MIDDLE - 1);
MAP_FLASH_CTL_A_UNPROTECT_MEMORY(INFO_FLASH_MIDDLE, INFO_FLASH_MIDDLE +
MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE() - 1);
}
/* Lock all Flash sectors */
void lock_all_flash_sectors(void)
{
MAP_FLASH_CTL_A_PROTECT_MEMORY(FLASH_BASE, FLASH_BASE +
MAP_SYS_CTL_A_GET_FLASH_SIZE() - 1);
MAP_FLASH_CTL_A_PROTECT_MEMORY(INFO_FLASH_START, INFO_FLASH_START +
MAP_SYS_CTL_A_GET_INFO_FLASH_SIZE() - 1);
}
/* Force DCO frequency range */
void __cs_set_dco_frequency_range(uint32_t dco_freq)
{
/* Unlocking the CS Module */
CS->KEY = CS_KEY_VAL;
/* Resetting Tuning Parameters and Setting the frequency */
CS->CTL0 = (CS->CTL0 & ~CS_CTL0_DCORSEL_MASK) | dco_freq;
/* Locking the CS Module */
CS->KEY = 0;
}
/* Exit flash programming */
void msp432_flash_exit(void)
{
bool success = false;
/* Restore modified registers, in reverse order */
__cs_set_dco_frequency_range(CS_DCO_FREQUENCY_3);
MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK0,
BACKUP_PARAMS->BANK0_WAIT_RESTORE);
MAP_FLASH_CTL_A_SET_WAIT_STATE(FLASH_A_BANK1,
BACKUP_PARAMS->BANK1_WAIT_RESTORE);
success = MAP_PCM_SET_POWER_STATE(BACKUP_PARAMS->PCM_VCORE_LEVEL_RESTORE);
success &= MAP_PCM_SET_CORE_VOLTAGE_LEVEL(
BACKUP_PARAMS->VCORE_LEVEL_RESTORE);
__cs_set_dco_frequency_range(BACKUP_PARAMS->CS_DC0_FREQ_RESTORE);
/* Point to vector table in Flash */
SCB->VTOR = (uint32_t)0x00000000;
if (!success)
FLASH_LOADER->RETURN_CODE = FLASH_ERROR;
else
FLASH_LOADER->RETURN_CODE = FLASH_SUCCESS;
}
static bool program_device(void *src, void *dest, uint32_t length)
{
uint32_t dst_address = (uint32_t)dest;
/* Flash main memory first, then information memory */
if ((dst_address < INFO_FLASH_START) && ((dst_address + length) >
INFO_FLASH_START)) {
uint32_t block_length = INFO_FLASH_START - dst_address;
uint32_t src_address = (uint32_t)src;
/* Main memory block */
bool success = MAP_FLASH_CTL_A_PROGRAM_MEMORY(src, dest, block_length);
src_address = src_address + block_length;
block_length = length - block_length;
/* Information memory block */
success &= MAP_FLASH_CTL_A_PROGRAM_MEMORY((void *)src_address,
(void *)INFO_FLASH_START, block_length);
return success;
} else
return MAP_FLASH_CTL_A_PROGRAM_MEMORY(src, dest, length);
}

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/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
#define OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Register map for FLASH_CTRL peripheral (FLASH_CTRL) */
struct flash_ctrl {
volatile uint32_t FMA; /* Flash Memory Address */
volatile uint32_t FMD; /* Flash Memory Data */
volatile uint32_t FMC; /* Flash Memory Control */
volatile uint32_t FCRIS; /* Flash Controller Raw Interrupt Status */
volatile uint32_t FCIM; /* Flash Controller Interrupt Mask */
volatile uint32_t FCMISC; /* Flash Cont. Masked Int. Status and Clear */
volatile uint32_t RESERVED0[2];
volatile uint32_t FMC2; /* Flash Memory Control 2 */
volatile uint32_t RESERVED1[3];
volatile uint32_t FWBVAL; /* Flash Write Buffer Valid */
volatile uint32_t RESERVED2[2];
volatile uint32_t FLPEKEY; /* Flash Program/Erase Key */
volatile uint32_t RESERVED3[48];
volatile uint32_t FWBN[32]; /* Flash Write Buffer n */
};
/* Register map for SYSCTL peripheral (SYSCTL) */
struct sys_ctrl {
volatile uint32_t DID0; /* Device Identification 0 */
volatile uint32_t DID1; /* Device Identification 1 */
volatile uint32_t RESERVED0[12];
volatile uint32_t PTBOCTL; /* Power-Temp Brown Out Control */
volatile uint32_t RESERVED1[5];
volatile uint32_t RIS; /* Raw Interrupt Status */
volatile uint32_t IMC; /* Interrupt Mask Control */
volatile uint32_t MISC; /* Masked Interrupt Status and Clear */
volatile uint32_t RESC; /* Reset Cause */
volatile uint32_t PWRTC; /* Power-Temperature Cause */
volatile uint32_t NMIC; /* NMI Cause Register */
volatile uint32_t RESERVED2[5];
volatile uint32_t MOSCCTL; /* Main Oscillator Control */
volatile uint32_t RESERVED3[12];
volatile uint32_t RSCLKCFG; /* Run and Sleep Mode Configuration Register */
volatile uint32_t RESERVED4[3];
volatile uint32_t MEMTIM0; /* Memory Timing Register 0 for Main Flash */
volatile uint32_t RESERVED5[29];
volatile uint32_t ALTCLKCFG; /* Alternate Clock Configuration */
volatile uint32_t RESERVED6[2];
union {
volatile uint32_t DSLPCLKCFG; /* Deep Sleep Clock Configuration */
volatile uint32_t DSCLKCFG; /* Deep Sleep Clock Register */
};
volatile uint32_t DIVSCLK; /* Divisor and Source Clock Configuration */
volatile uint32_t SYSPROP; /* System Properties */
volatile uint32_t PIOSCCAL; /* Precision Internal Oscillator Calibration */
volatile uint32_t PIOSCSTAT; /* Precision Internal Oscillator Statistics */
volatile uint32_t RESERVED7[2];
volatile uint32_t PLLFREQ0; /* PLL Frequency 0 */
volatile uint32_t PLLFREQ1; /* PLL Frequency 1 */
volatile uint32_t PLLSTAT; /* PLL Status */
volatile uint32_t RESERVED8[7];
volatile uint32_t SLPPWRCFG; /* Sleep Power Configuration */
volatile uint32_t DSLPPWRCFG; /* Deep-Sleep Power Configuration */
volatile uint32_t RESERVED9[4];
volatile uint32_t NVMSTAT; /* Non-Volatile Memory Information */
volatile uint32_t RESERVED10[4];
volatile uint32_t LDOSPCTL; /* LDO Sleep Power Control */
volatile uint32_t RESERVED11;
volatile uint32_t LDODPCTL; /* LDO Deep-Sleep Power Control */
volatile uint32_t RESERVED12[6];
volatile uint32_t RESBEHAVCTL; /* Reset Behavior Control Register */
volatile uint32_t RESERVED13[6];
volatile uint32_t HSSR; /* Hardware System Service Request */
volatile uint32_t RESERVED14[34];
volatile uint32_t USBPDS; /* USB Power Domain Status */
volatile uint32_t USBMPC; /* USB Memory Power Control */
volatile uint32_t EMACPDS; /* Ethernet MAC Power Domain Status */
volatile uint32_t EMACMPC; /* Ethernet MAC Memory Power Control */
volatile uint32_t RESERVED15;
volatile uint32_t LCDMPC; /* LCD Memory Power Control */
volatile uint32_t RESERVED16[26];
volatile uint32_t PPWD; /* Watchdog Timer Peripheral Present */
volatile uint32_t PPTIMER; /* General-Purpose Timer Peripheral Present */
volatile uint32_t PPGPIO; /* General-Purpose I/O Peripheral Present */
volatile uint32_t PPDMA; /* Micro DMA Peripheral Present */
volatile uint32_t PPEPI; /* EPI Peripheral Present */
volatile uint32_t PPHIB; /* Hibernation Peripheral Present */
volatile uint32_t PPUART; /* UART Peripheral Present */
volatile uint32_t PPSSI; /* Synchronous Serial Inter. Periph. Present */
volatile uint32_t PPI2C; /* Inter-Integrated Circuit Periph. Present */
volatile uint32_t RESERVED17;
volatile uint32_t PPUSB; /* Universal Serial Bus Peripheral Present */
volatile uint32_t RESERVED18;
volatile uint32_t PPEPHY; /* Ethernet PHY Peripheral Present */
volatile uint32_t PPCAN; /* Controller Area Network Periph. Present */
volatile uint32_t PPADC; /* Analog-to-Dig. Converter Periph. Present */
volatile uint32_t PPACMP; /* Analog Comparator Peripheral Present */
volatile uint32_t PPPWM; /* Pulse Width Modulator Peripheral Present */
volatile uint32_t PPQEI; /* Quadrature Encoder Inter. Periph. Present */
volatile uint32_t RESERVED19[4];
volatile uint32_t PPEEPROM; /* EEPROM Peripheral Present */
volatile uint32_t RESERVED20[6];
volatile uint32_t PPCCM; /* CRC/Cryptographic Modules Periph. Present */
volatile uint32_t RESERVED21[6];
volatile uint32_t PPLCD; /* LCD Peripheral Present */
volatile uint32_t RESERVED22;
volatile uint32_t PPOWIRE; /* 1-Wire Peripheral Present */
volatile uint32_t PPEMAC; /* Ethernet MAC Peripheral Present */
volatile uint32_t RESERVED23[88];
volatile uint32_t SRWD; /* Watchdog Timer Software Reset */
volatile uint32_t SRTIMER; /* General-Purpose Timer Software Reset */
volatile uint32_t SRGPIO; /* General-Purpose I/O Software Reset */
volatile uint32_t SRDMA; /* Micro Direct Memory Access Software Reset */
volatile uint32_t SREPI; /* EPI Software Reset */
volatile uint32_t SRHIB; /* Hibernation Software Reset */
volatile uint32_t SRUART; /* UART Software Reset */
volatile uint32_t SRSSI; /* Synchronous Serial Inter. Software Reset */
volatile uint32_t SRI2C; /* Inter-Integrated Circuit Software Reset */
volatile uint32_t RESERVED24;
volatile uint32_t SRUSB; /* Universal Serial Bus Software Reset */
volatile uint32_t RESERVED25;
volatile uint32_t SREPHY; /* Ethernet PHY Software Reset */
volatile uint32_t SRCAN; /* Controller Area Network Software Reset */
volatile uint32_t SRADC; /* Analog-to-Dig. Converter Software Reset */
volatile uint32_t SRACMP; /* Analog Comparator Software Reset */
volatile uint32_t SRPWM; /* Pulse Width Modulator Software Reset */
volatile uint32_t SRQEI; /* Quadrature Encoder Inter. Software Reset */
volatile uint32_t RESERVED26[4];
volatile uint32_t SREEPROM; /* EEPROM Software Reset */
volatile uint32_t RESERVED27[6];
volatile uint32_t SRCCM; /* CRC/Cryptographic Modules Software Reset */
volatile uint32_t RESERVED28[6];
volatile uint32_t SRLCD; /* LCD Controller Software Reset */
volatile uint32_t RESERVED29;
volatile uint32_t SROWIRE; /* 1-Wire Software Reset */
volatile uint32_t SREMAC; /* Ethernet MAC Software Reset */
volatile uint32_t RESERVED30[24];
volatile uint32_t RCGCWD; /* Watchdog Run Mode Clock Gating Control */
};
/* Peripheral Memory Map */
#define FLASH_CTRL_BASE 0x400FD000UL
#define SYSCTL_BASE 0x400FE000UL
/* Peripheral Declarations */
#define FLASH_CTRL ((struct flash_ctrl *) FLASH_CTRL_BASE)
#define SYSCTL ((struct sys_ctrl *) SYSCTL_BASE)
/* The following are defines for the bit fields in the FLASH_FMC register. */
#define FLASH_FMC_WRKEY 0xA4420000 /* FLASH write key */
#define FLASH_FMC_COMT 0x00000008 /* Commit Register Value */
#define FLASH_FMC_MERASE 0x00000004 /* Mass Erase Flash Memory */
#define FLASH_FMC_ERASE 0x00000002 /* Erase a Page of Flash Memory */
#define FLASH_FMC_WRITE 0x00000001 /* Write a Word into Flash Memory */
/* The following are defines for the bit fields in the FLASH_FCRIS register. */
#define FLASH_FCRIS_PROGRIS 0x00002000 /* Program Verify Raw Interrupt Status */
#define FLASH_FCRIS_ERRIS 0x00000800 /* Erase Verify Raw Interrupt Status */
#define FLASH_FCRIS_INVDRIS 0x00000400 /* Invalid Data Raw Interrupt Status */
#define FLASH_FCRIS_VOLTRIS 0x00000200 /* Pump Voltage Raw Interrupt Status */
#define FLASH_FCRIS_ERIS 0x00000004 /* EEPROM Raw Interrupt Status */
#define FLASH_FCRIS_PRIS 0x00000002 /* Programming Raw Interrupt Status */
#define FLASH_FCRIS_ARIS 0x00000001 /* Access Raw Interrupt Status */
/* The following are defines for the bit fields in the FLASH_FCIM register. */
#define FLASH_FCIM_PROGMASK 0x00002000 /* PROGVER Interrupt Mask */
#define FLASH_FCIM_ERMASK 0x00000800 /* ERVER Interrupt Mask */
#define FLASH_FCIM_INVDMASK 0x00000400 /* Invalid Data Interrupt Mask */
#define FLASH_FCIM_VOLTMASK 0x00000200 /* VOLT Interrupt Mask */
#define FLASH_FCIM_EMASK 0x00000004 /* EEPROM Interrupt Mask */
#define FLASH_FCIM_PMASK 0x00000002 /* Programming Interrupt Mask */
#define FLASH_FCIM_AMASK 0x00000001 /* Access Interrupt Mask */
/* The following are defines for the bit fields in the FLASH_FCMISC register. */
#define FLASH_FCMISC_PROGMISC 0x00002000 /* PROGVER Interrupt Status/Clear */
#define FLASH_FCMISC_ERMISC 0x00000800 /* ERVER Interrupt Status/Clear */
#define FLASH_FCMISC_INVDMISC 0x00000400 /* Invalid Data Int. Status/Clear */
#define FLASH_FCMISC_VOLTMISC 0x00000200 /* VOLT Interrupt Status/Clear */
#define FLASH_FCMISC_EMISC 0x00000004 /* EEPROM Interrupt Status/Clear */
#define FLASH_FCMISC_PMISC 0x00000002 /* Programming Int. Status/Clear */
#define FLASH_FCMISC_AMISC 0x00000001 /* Access Interrupt Status/Clear */
/* The following are defines for the bit fields in the FLASH_FMC2 register. */
#define FLASH_FMC2_WRBUF 0x00000001 /* Buffered Flash Memory Write */
/* The following are defines for the bit fields in the SYSCTL_RCGCWD reg. */
#define SYSCTL_RCGCWD_R1 0x00000002 /* Watchdog 1 Run Mode Clock Gating Cont. */
#define SYSCTL_RCGCWD_R0 0x00000001 /* Watchdog 0 Run Mode Clock Gating Cont. */
#ifdef __cplusplus
}
#endif
#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432E4X_H */

149
contrib/loaders/flash/msp432/msp432e4x/msp432e4x.lds Normal file
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@ -0,0 +1,149 @@
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
MEMORY {
MAIN_FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00100000
SRAM_CODE_0(RWX): ORIGIN = 0x20000000, LENGTH = 0x00000110
SRAM_CODE_1(RWX): ORIGIN = 0x20000110, LENGTH = 0x00000030
SRAM_CODE_2(RWX): ORIGIN = 0x20000150, LENGTH = 0x00000040
SRAM_CODE_3(RWX): ORIGIN = 0x20000190, LENGTH = 0x00000F70
SRAM_CODE_4(RWX): ORIGIN = 0x20001170, LENGTH = 0x00000200
SRAM_DATA (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000
}
REGION_ALIAS("REGION_INTVECT", SRAM_CODE_0);
REGION_ALIAS("REGION_RESET", SRAM_CODE_1);
REGION_ALIAS("REGION_DESCRIPTOR", SRAM_CODE_2);
REGION_ALIAS("REGION_TEXT", SRAM_CODE_3);
REGION_ALIAS("REGION_BSS", SRAM_CODE_3);
REGION_ALIAS("REGION_DATA", SRAM_DATA);
REGION_ALIAS("REGION_STACK", SRAM_CODE_4);
REGION_ALIAS("REGION_HEAP", SRAM_DATA);
REGION_ALIAS("REGION_ARM_EXIDX", SRAM_CODE_3);
REGION_ALIAS("REGION_ARM_EXTAB", SRAM_CODE_3);
SECTIONS {
/* section for the interrupt vector area */
.intvecs : {
KEEP (*(.intvecs))
} > REGION_INTVECT
PROVIDE (_vtable_base_address =
DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000);
.vtable (_vtable_base_address) : AT (_vtable_base_address) {
KEEP (*(.vtable))
} > REGION_DATA
.descriptor :{
FILL(0x00000000);
. = ORIGIN(REGION_DESCRIPTOR) + LENGTH(REGION_DESCRIPTOR) - 1;
BYTE(0x00);
__ROM_AT = .;
} > REGION_DESCRIPTOR
.reset : {
KEEP(*(.reset))
} > REGION_RESET AT> REGION_RESET
.text : {
CREATE_OBJECT_SYMBOLS
KEEP (*(.text))
*(.text.*)
. = ALIGN(0x4);
KEEP (*(.ctors))
. = ALIGN(0x4);
KEEP (*(.dtors))
. = ALIGN(0x4);
__init_array_start = .;
KEEP (*(.init_array*))
__init_array_end = .;
KEEP (*(.init))
KEEP (*(.fini*))
} > REGION_TEXT AT> REGION_TEXT
.rodata : {
*(.rodata)
*(.rodata.*)
} > REGION_TEXT AT> REGION_TEXT
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
.ARM.extab : {
KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*))
} > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
__etext = .;
.data : {
__data_load__ = LOADADDR (.data);
__data_start__ = .;
KEEP (*(.data))
KEEP (*(.data*))
. = ALIGN (4);
__data_end__ = .;
} > REGION_DATA AT> REGION_TEXT
.bss : {
__bss_start__ = .;
*(.shbss)
KEEP (*(.bss))
*(.bss.*)
*(COMMON)
. = ALIGN (4);
__bss_end__ = .;
} > REGION_BSS AT> REGION_BSS
.heap : {
__heap_start__ = .;
end = __heap_start__;
_end = end;
__end = end;
KEEP (*(.heap))
__heap_end__ = .;
__HeapLimit = __heap_end__;
} > REGION_HEAP AT> REGION_HEAP
.stack (NOLOAD) : ALIGN(0x8) {
_stack = .;
KEEP(*(.stack))
} > REGION_STACK AT> REGION_STACK
__stack_top = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK);
PROVIDE(__stack = __stack_top);
}

245
contrib/loaders/flash/msp432/msp432e4x_algo.inc Normal file
View File

@ -0,0 +1,245 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x34,0x0f,0x00,0x20,0x00,0x00,0x00,0x00,0xf8,0x0a,0x00,0x20,0x08,0xb5,0x08,0x4b,
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0x08,0x20,0x00,0x20,

102
contrib/loaders/flash/msp432/msp432p401x.h Normal file
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@ -0,0 +1,102 @@
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H
#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
#define __MCU_HAS_FLCTL__ /* Module FLCTL is available */
/* Device and peripheral memory map */
#define FLASH_BASE ((uint32_t)0x00000000) /* Flash memory start address */
#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM memory start address */
#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripherals start address */
#define CS_BASE (PERIPH_BASE + 0x00010400) /* Address of module CS regs. */
#define DIO_BASE (PERIPH_BASE + 0x00004C00) /* Address of module DIO regs. */
/* Register map for Clock Signal peripheral (CS) */
struct cs {
volatile uint32_t KEY; /* Key Register */
volatile uint32_t CTL0; /* Control 0 Register */
volatile uint32_t CTL1; /* Control 1 Register */
volatile uint32_t CTL2; /* Control 2 Register */
volatile uint32_t CTL3; /* Control 3 Register */
};
/* Register map for DIO port (odd interrupt) */
struct dio_port_odd_int {
volatile uint8_t IN; /* Port Input */
uint8_t RESERVED0;
volatile uint8_t OUT; /* Port Output */
};
/* Register map for DIO port (even interrupt) */
struct dio_port_even_int {
uint8_t RESERVED0;
volatile uint8_t IN; /* Port Input */
uint8_t RESERVED1;
volatile uint8_t OUT; /* Port Output */
};
/* Peripheral declarations */
#define CS ((struct cs *) CS_BASE)
#define P3 ((struct dio_port_odd_int *) (DIO_BASE + 0x0020))
#define P6 ((struct dio_port_even_int *) (DIO_BASE + 0x0040))
/* Peripheral bit definitions */
/* DCORSEL Bit Mask */
#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000)
/* Nominal DCO Frequency Range (MHz): 2 to 4 */
#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000)
/* Nominal DCO Frequency Range (MHz): 16 to 32 */
#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000)
/* CS control key value */
#define CS_KEY_VAL ((uint32_t)0x0000695A)
/* Protects Sector 0 from program or erase */
#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001)
/* Protects Sector 1 from program or erase */
#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002)
#ifdef __cplusplus
}
#endif
#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P401X_H */

151
contrib/loaders/flash/msp432/msp432p401x/msp432p401x.lds Normal file
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@ -0,0 +1,151 @@
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
MEMORY {
MAIN_FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00040000
INFO_FLASH (RX) : ORIGIN = 0x00200000, LENGTH = 0x00004000
SRAM_CODE_0(RWX): ORIGIN = 0x01000000, LENGTH = 0x00000110
SRAM_CODE_1(RWX): ORIGIN = 0x01000110, LENGTH = 0x00000030
SRAM_CODE_2(RWX): ORIGIN = 0x01000150, LENGTH = 0x00000040
SRAM_CODE_3(RWX): ORIGIN = 0x01000190, LENGTH = 0x00000F70
SRAM_CODE_4(RWX): ORIGIN = 0x01001170, LENGTH = 0x00000200
SRAM_DATA (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000
}
REGION_ALIAS("REGION_INTVECT", SRAM_CODE_0);
REGION_ALIAS("REGION_RESET", SRAM_CODE_1);
REGION_ALIAS("REGION_DESCRIPTOR", SRAM_CODE_2);
REGION_ALIAS("REGION_TEXT", SRAM_CODE_3);
REGION_ALIAS("REGION_BSS", SRAM_CODE_3);
REGION_ALIAS("REGION_DATA", SRAM_DATA);
REGION_ALIAS("REGION_STACK", SRAM_CODE_4);
REGION_ALIAS("REGION_HEAP", SRAM_DATA);
REGION_ALIAS("REGION_ARM_EXIDX", SRAM_CODE_3);
REGION_ALIAS("REGION_ARM_EXTAB", SRAM_CODE_3);
SECTIONS {
/* section for the interrupt vector area */
.intvecs : {
KEEP (*(.intvecs))
} > REGION_INTVECT
PROVIDE (_vtable_base_address =
DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000);
.vtable (_vtable_base_address) : AT (_vtable_base_address) {
KEEP (*(.vtable))
} > REGION_DATA
.descriptor :{
FILL(0x00000000);
. = ORIGIN(REGION_DESCRIPTOR) + LENGTH(REGION_DESCRIPTOR) - 1;
BYTE(0x00);
__ROM_AT = .;
} > REGION_DESCRIPTOR
.reset : {
KEEP(*(.reset))
} > REGION_RESET AT> REGION_RESET
.text : {
CREATE_OBJECT_SYMBOLS
KEEP (*(.text))
*(.text.*)
. = ALIGN(0x4);
KEEP (*(.ctors))
. = ALIGN(0x4);
KEEP (*(.dtors))
. = ALIGN(0x4);
__init_array_start = .;
KEEP (*(.init_array*))
__init_array_end = .;
KEEP (*(.init))
KEEP (*(.fini*))
} > REGION_TEXT AT> REGION_TEXT
.rodata : {
*(.rodata)
*(.rodata.*)
} > REGION_TEXT AT> REGION_TEXT
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
.ARM.extab : {
KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*))
} > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
__etext = .;
.data : {
__data_load__ = LOADADDR (.data);
__data_start__ = .;
KEEP (*(.data))
KEEP (*(.data*))
. = ALIGN (4);
__data_end__ = .;
} > REGION_DATA AT> REGION_TEXT
.bss : {
__bss_start__ = .;
*(.shbss)
KEEP (*(.bss))
*(.bss.*)
*(COMMON)
. = ALIGN (4);
__bss_end__ = .;
} > REGION_BSS AT> REGION_BSS
.heap : {
__heap_start__ = .;
end = __heap_start__;
_end = end;
__end = end;
KEEP (*(.heap))
__heap_end__ = .;
__HeapLimit = __heap_end__;
} > REGION_HEAP AT> REGION_HEAP
.stack (NOLOAD) : ALIGN(0x8) {
_stack = .;
KEEP(*(.stack))
} > REGION_STACK AT> REGION_STACK
__stack_top = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK);
PROVIDE(__stack = __stack_top);
}

242
contrib/loaders/flash/msp432/msp432p401x_algo.inc Normal file
View File

@ -0,0 +1,242 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0x45,0xea,0x05,0x45,0x19,0xd9,0x03,0xf1,0x10,0x02,0x26,0x46,0x10,0x3e,0x0f,0x2e,
0x42,0xf8,0x10,0x5c,0x42,0xf8,0x0c,0x5c,0x42,0xf8,0x08,0x5c,0x42,0xf8,0x04,0x5c,
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0x0f,0x04,0x10,0x32,0x03,0x2c,0x13,0x44,0x0d,0xd9,0x1e,0x46,0x22,0x46,0x04,0x3a,
0x03,0x2a,0x46,0xf8,0x04,0x5b,0xfa,0xd8,0x22,0x1f,0x22,0xf0,0x03,0x02,0x04,0x32,
0x13,0x44,0x04,0xf0,0x03,0x04,0x2c,0xb1,0xc9,0xb2,0x1c,0x44,0x03,0xf8,0x01,0x1b,
0xa3,0x42,0xfb,0xd1,0x70,0xbc,0x70,0x47,0x14,0x46,0x03,0x46,0xc2,0xe7,0x00,0xbf,
0x2d,0xe9,0xf0,0x47,0x25,0x4c,0x25,0x68,0xd5,0xf8,0x48,0x41,0x06,0x46,0x88,0x46,
0x92,0x46,0x99,0x46,0xcc,0xb3,0x60,0x68,0x1f,0x28,0x18,0xdc,0x43,0x1c,0x7e,0xb1,
0x04,0xeb,0x80,0x05,0x01,0x21,0xc5,0xf8,0x88,0xa0,0xd4,0xf8,0x88,0x71,0x01,0xfa,
0x00,0xf2,0x17,0x43,0x02,0x2e,0xc4,0xf8,0x88,0x71,0xc5,0xf8,0x08,0x91,0x1e,0xd0,
0x02,0x30,0x63,0x60,0x44,0xf8,0x20,0x80,0x00,0x20,0xbd,0xe8,0xf0,0x87,0x14,0x4b,
0x03,0xb3,0x4f,0xf4,0xc8,0x70,0xaf,0xf3,0x00,0x80,0x04,0x46,0xd0,0xb1,0xd5,0xf8,
0x48,0x31,0x00,0x27,0x80,0xe8,0x88,0x00,0xc5,0xf8,0x48,0x41,0x38,0x46,0x01,0x23,
0xc4,0xf8,0x88,0x71,0xc4,0xf8,0x8c,0x71,0x00,0x2e,0xe1,0xd0,0xd0,0xe7,0xd4,0xf8,
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0x48,0x41,0xc0,0xe7,0x4f,0xf0,0xff,0x30,0xbd,0xe8,0xf0,0x87,0xcc,0x0a,0x00,0x01,
0x00,0x00,0x00,0x00,0x02,0x4b,0x13,0xb1,0x02,0x48,0xff,0xf7,0x07,0xbf,0x70,0x47,
0x00,0x00,0x00,0x00,0xc9,0x02,0x00,0x01,0x2d,0xe9,0xf0,0x4f,0x31,0x4b,0x83,0xb0,
0x1b,0x68,0x00,0x93,0x03,0xf5,0xa4,0x73,0x81,0x46,0x0e,0x46,0x01,0x93,0x00,0x9b,
0xd3,0xf8,0x48,0x71,0x27,0xb3,0xdd,0xf8,0x04,0xa0,0x7c,0x68,0x65,0x1e,0x0e,0xd4,
0x01,0x34,0x07,0xeb,0x84,0x04,0x4f,0xf0,0x00,0x08,0xe6,0xb1,0xd4,0xf8,0x00,0x31,
0xb3,0x42,0x18,0xd0,0x01,0x3d,0x6b,0x1c,0xa4,0xf1,0x04,0x04,0xf5,0xd1,0x22,0x4b,
0x73,0xb1,0x7b,0x68,0x00,0x2b,0x36,0xd1,0x3b,0x68,0x00,0x2b,0x34,0xd0,0x38,0x46,
0xca,0xf8,0x00,0x30,0xaf,0xf3,0x00,0x80,0xda,0xf8,0x00,0x70,0x00,0x2f,0xdc,0xd1,
0x03,0xb0,0xbd,0xe8,0xf0,0x8f,0x7b,0x68,0x22,0x68,0x01,0x3b,0xab,0x42,0x0c,0xbf,
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0x04,0xb0,0x01,0x21,0xa9,0x40,0x19,0x42,0x08,0xd1,0x90,0x47,0x7b,0x68,0x5b,0x45,
0xbd,0xd1,0xda,0xf8,0x00,0x30,0xbb,0x42,0xcc,0xd0,0xb8,0xe7,0xd7,0xf8,0x8c,0x31,
0x19,0x42,0x04,0xd1,0x48,0x46,0xd4,0xf8,0x80,0x10,0x90,0x47,0xee,0xe7,0xd4,0xf8,
0x80,0x00,0x90,0x47,0xea,0xe7,0x3b,0x68,0xba,0x46,0x1f,0x46,0x00,0x2f,0xac,0xd1,
0xce,0xe7,0x00,0xbf,0xcc,0x0a,0x00,0x01,0x00,0x00,0x00,0x00,0xfe,0xe7,0x00,0xbf,
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0x98,0x47,0x33,0x68,0x28,0x60,0x9b,0x6d,0x01,0x20,0x98,0x47,0x3b,0x68,0x68,0x60,
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0xce,0x22,0x5a,0x60,0xf8,0xbd,0x07,0x4a,0x5a,0x60,0xf8,0xbd,0x1c,0x08,0x00,0x02,
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0x50,0x01,0x00,0x20,0x00,0xad,0xde,0x00,0x2d,0xe9,0xf8,0x4f,0x4e,0x4c,0x25,0x69,
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0x38,0x91,0x4f,0xf0,0x00,0x08,0xdb,0xf8,0x00,0x30,0xb5,0xf5,0x80,0x5f,0x1b,0x69,
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0x4f,0xf4,0x80,0x56,0x00,0x25,0x98,0x47,0xdb,0xf8,0x00,0x30,0x4f,0xf0,0xff,0x31,
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0x98,0x47,0x23,0x6a,0x0b,0x2b,0x03,0xd1,0x60,0xe0,0xa3,0x69,0xd9,0x06,0x02,0xd4,
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0x00,0x20,0x43,0xf0,0x01,0x03,0x63,0x61,0x93,0x6a,0x39,0x46,0x4f,0xf0,0x20,0x20,
0x32,0x46,0x98,0x47,0x99,0xf8,0x03,0x30,0x03,0xf0,0xef,0x03,0x89,0xf8,0x03,0x30,
0x63,0x69,0x23,0xf0,0x11,0x03,0x80,0x46,0x37,0x44,0x63,0x61,0xdb,0xf8,0x00,0x30,
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0xb8,0xf1,0x00,0x0f,0x29,0xd0,0x00,0x2d,0x9d,0xd1,0x17,0x4b,0x40,0xf6,0xce,0x22,
0x5a,0x60,0xbd,0xe8,0xf8,0x8f,0xa3,0x69,0xdb,0x06,0xd7,0xd5,0xa3,0x69,0xdb,0xf8,
0x00,0x20,0x12,0x48,0x43,0xf0,0x01,0x03,0xa3,0x61,0x93,0x6a,0x39,0x46,0x32,0x46,
0x98,0x47,0x9a,0xf8,0x02,0x30,0x03,0xf0,0xbf,0x03,0x8a,0xf8,0x02,0x30,0xa3,0x69,
0x23,0xf0,0x11,0x03,0x80,0x46,0x37,0x44,0xa3,0x61,0xbf,0xe7,0xdb,0xf8,0x00,0x30,
0x03,0x21,0x1b,0x69,0x04,0x20,0x98,0x47,0x9a,0xe7,0x03,0x4b,0x4d,0xf6,0xad,0x62,
0x5a,0x60,0xbd,0xe8,0xf8,0x8f,0x00,0xbf,0x50,0x01,0x00,0x20,0x00,0x30,0x00,0x20,
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0xda,0x07,0x70,0xb5,0x14,0xd4,0x11,0x4c,0xe3,0x69,0x9b,0x07,0x00,0xd4,0x70,0xbd,
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0xf5,0xd1,0x2b,0x68,0x04,0x20,0x1b,0x69,0x03,0x21,0xbd,0xe8,0x70,0x40,0x18,0x47,
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0x3a,0x68,0xdf,0xf8,0x84,0x90,0x46,0xf6,0x5a,0x18,0xc4,0xf8,0x00,0x80,0x63,0x68,
0x23,0xf4,0xe0,0x23,0x00,0x26,0x43,0xf4,0x80,0x33,0x63,0x60,0x26,0x60,0x53,0x6d,
0x30,0x46,0x98,0x47,0x3b,0x68,0x69,0x68,0x5b,0x6d,0x01,0x20,0x98,0x47,0xd9,0xf8,
0x00,0x30,0x68,0x7b,0x9b,0x69,0x98,0x47,0xd9,0xf8,0x00,0x30,0x07,0x46,0x1b,0x68,
0x28,0x7b,0x98,0x47,0xc4,0xf8,0x00,0x80,0x63,0x68,0xaa,0x68,0x0c,0x49,0x23,0xf4,
0xe0,0x23,0x13,0x43,0x63,0x60,0x26,0x60,0x0a,0x4b,0x8e,0x60,0x28,0xb1,0x27,0xb1,
0x40,0xf6,0xce,0x22,0x5a,0x60,0xbd,0xe8,0xf8,0x83,0x4d,0xf6,0xad,0x62,0x5a,0x60,
0xbd,0xe8,0xf8,0x83,0x00,0x04,0x01,0x40,0x80,0x01,0x00,0x20,0x1c,0x08,0x00,0x02,
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0x21,0x09,0x00,0x01,0x4f,0x0a,0x00,0x01,0x4f,0x0a,0x00,0x01,0x4f,0x0a,0x00,0x01,
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0x13,0x09,0x00,0x01,0x4f,0x0a,0x00,0x01,0x4f,0x0a,0x00,0x01,0x4f,0x0a,0x00,0x01,
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0x05,0x09,0x00,0x01,0x01,0x23,0x63,0x60,0xff,0xf7,0x86,0xfe,0x00,0x23,0x23,0x60,
0xae,0xe7,0x01,0x23,0x63,0x60,0xff,0xf7,0x55,0xff,0x00,0x23,0x23,0x60,0xa7,0xe7,
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0x4f,0xf0,0x20,0x20,0x98,0x47,0x7b,0x69,0x2a,0x68,0x23,0xf0,0x11,0x03,0x7b,0x61,
0x53,0x69,0x06,0x46,0x4f,0xf0,0xff,0x31,0x01,0x20,0x98,0x47,0x2b,0x68,0x4f,0xf0,
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0x63,0x60,0xff,0xf7,0xb3,0xfe,0x05,0x26,0x2b,0x68,0x1b,0x6a,0x98,0x47,0x01,0x3e,
0x00,0x28,0x30,0xd1,0x00,0x2e,0xf7,0xd1,0x20,0x4b,0x63,0x60,0x2b,0x68,0x4f,0xf0,
0xff,0x31,0x5b,0x69,0x01,0x20,0x98,0x47,0x2b,0x68,0x4f,0xf0,0xff,0x31,0x5b,0x69,
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0x00,0x00,0x00,0x00,0xf4,0x22,0x00,0x20,0x5c,0x23,0x00,0x20,0xc4,0x23,0x00,0x20,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x20,0x00,0x20,

164
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/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#ifndef OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
#define OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/* Available Peripherals */
#define __MCU_HAS_FLCTL_A__ /* Module FLCTL_A is available */
#define __MCU_HAS_SYSCTL_A__ /* Module SYSCTL_A is available */
/* Device and Peripheral Memory Map */
#define FLASH_BASE ((uint32_t)0x00000000) /* Flash memory address */
#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripherals address */
#define CS_BASE (PERIPH_BASE + 0x00010400) /* Address of CS regs. */
#define PCM_BASE (PERIPH_BASE + 0x00010000) /* Address of PCM regs. */
#define RTC_C_BASE (PERIPH_BASE + 0x00004400) /* Address of RTC_C regs */
#define TLV_BASE ((uint32_t)0x00201000) /* Address of TLV regs. */
#define WDT_A_BASE (PERIPH_BASE + 0x00004800) /* Address of WDT_A regs */
#define BITBAND_PERI_BASE ((uint32_t)(0x42000000))
/*
* Peripherals with 8-bit or 16-bit register access allow only 8-bit or
* 16-bit bit band access, so cast to 8 bit always
*/
#define BITBAND_PERI(x, b) (*((volatile uint8_t *) (BITBAND_PERI_BASE + \
(((uint32_t)(uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
/* Register map for CLock Signal peripheral (CS) */
struct cs {
volatile uint32_t KEY; /* Key Register */
volatile uint32_t CTL0; /* Control 0 Register */
volatile uint32_t CTL1; /* Control 1 Register */
volatile uint32_t CTL2; /* Control 2 Register */
volatile uint32_t CTL3; /* Control 3 Register */
};
/* Register map for Power Control Module peripheral (PCM) */
struct pcm {
volatile uint32_t CTL0; /* Control 0 Register */
volatile uint32_t CTL1; /* Control 1 Register */
volatile uint32_t IE; /* Interrupt Enable Register */
volatile uint32_t IFG; /* Interrupt Flag Register */
volatile uint32_t CLRIFG; /* Clear Interrupt Flag Register */
};
/* Register map for Real-Time Clock peripheral (RTC_C) */
struct rtc_c {
volatile uint16_t CTL0; /* RTCCTL0 Register */
volatile uint16_t CTL13; /* RTCCTL13 Register */
volatile uint16_t OCAL; /* RTCOCAL Register */
volatile uint16_t TCMP; /* RTCTCMP Register */
volatile uint16_t PS0CTL; /* RTC Prescale Timer 0 Control Register */
volatile uint16_t PS1CTL; /* RTC Prescale Timer 1 Control Register */
volatile uint16_t PS; /* Real-Time Clock Prescale Timer Register */
volatile uint16_t IV; /* Real-Time Clock Interrupt Vector Register */
volatile uint16_t TIM0; /* RTCTIM0 Register Hexadecimal Format */
volatile uint16_t TIM1; /* Real-Time Clock Hour, Day of Week */
volatile uint16_t DATE; /* RTCDATE - Hexadecimal Format */
volatile uint16_t YEAR; /* RTCYEAR Register - Hexadecimal Format */
volatile uint16_t AMINHR; /* RTCMINHR - Hexadecimal Format */
volatile uint16_t ADOWDAY; /* RTCADOWDAY - Hexadecimal Format */
volatile uint16_t BIN2BCD; /* Binary-to-BCD Conversion Register */
volatile uint16_t BCD2BIN; /* BCD-to-Binary Conversion Register */
};
/* Register map for Watchdog Timer peripheral (WDT_A) */
struct wdt_a {
uint16_t RESERVED0[6];
volatile uint16_t CTL; /* Watchdog Timer Control Register */
};
/* Peripheral Declarations */
#define CS ((struct cs *) CS_BASE)
#define PCM ((struct pcm *) PCM_BASE)
#define RTC_C ((struct rtc_c *) RTC_C_BASE)
#define WDT_A ((struct wdt_a *) WDT_A_BASE)
/* Peripheral Register Bit Definitions */
/* DCORSEL Bit Mask */
#define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000)
/* Nominal DCO Frequency Range (MHz): 2 to 4 */
#define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000)
/* Nominal DCO Frequency Range (MHz): 16 to 32 */
#define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000)
/* CS control key value */
#define CS_KEY_VAL ((uint32_t)0x0000695A)
/* AMR Bit Mask */
#define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F)
/* LPMR Bit Mask */
#define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0)
/* LPM3.5. Core voltage setting 0. */
#define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0)
/* LPM4.5 */
#define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0)
/* CPM Bit Offset */
#define PCM_CTL0_CPM_OFS (8)
/* CPM Bit Mask */
#define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00)
/* PCMKEY Bit Mask */
#define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000)
/* PMR_BUSY Bit Offset */
#define PCM_CTL1_PMR_BUSY_OFS (8)
/* RTCKEY Bit Offset */
#define RTC_C_CTL0_KEY_OFS (8)
/* RTCKEY Bit Mask */
#define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00)
/* RTCHOLD Bit Offset */
#define RTC_C_CTL13_HOLD_OFS (6)
/* RTC_C Key Value for RTC_C write access */
#define RTC_C_KEY ((uint16_t)0xA500)
/* Watchdog timer hold */
#define WDT_A_CTL_HOLD ((uint16_t)0x0080)
/* WDT Key Value for WDT write access */
#define WDT_A_CTL_PW ((uint16_t)0x5A00)
/* Address of BSL API table */
#define BSL_API_TABLE_ADDR ((uint32_t)0x00202000)
#ifdef __cplusplus
}
#endif
#endif /* OPENOCD_LOADERS_FLASH_MSP432_MSP432P411X_H */

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/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
MEMORY {
MAIN_FLASH (RX) : ORIGIN = 0x00000000, LENGTH = 0x00200000
INFO_FLASH (RX) : ORIGIN = 0x00200000, LENGTH = 0x00008000
SRAM_CODE_0(RWX): ORIGIN = 0x01000000, LENGTH = 0x00000110
SRAM_CODE_1(RWX): ORIGIN = 0x01000110, LENGTH = 0x00000030
SRAM_CODE_2(RWX): ORIGIN = 0x01000150, LENGTH = 0x00000040
SRAM_CODE_3(RWX): ORIGIN = 0x01000190, LENGTH = 0x00001E70
SRAM_CODE_4(RWX): ORIGIN = 0x01002000, LENGTH = 0x00000200
SRAM_DATA (RW) : ORIGIN = 0x20002000, LENGTH = 0x00001000
}
REGION_ALIAS("REGION_INTVECT", SRAM_CODE_0);
REGION_ALIAS("REGION_RESET", SRAM_CODE_1);
REGION_ALIAS("REGION_DESCRIPTOR", SRAM_CODE_2);
REGION_ALIAS("REGION_TEXT", SRAM_CODE_3);
REGION_ALIAS("REGION_BSS", SRAM_CODE_3);
REGION_ALIAS("REGION_DATA", SRAM_DATA);
REGION_ALIAS("REGION_STACK", SRAM_CODE_4);
REGION_ALIAS("REGION_HEAP", SRAM_DATA);
REGION_ALIAS("REGION_ARM_EXIDX", SRAM_CODE_3);
REGION_ALIAS("REGION_ARM_EXTAB", SRAM_CODE_3);
SECTIONS {
/* section for the interrupt vector area */
.intvecs : {
KEEP (*(.intvecs))
} > REGION_INTVECT
PROVIDE (_vtable_base_address =
DEFINED(_vtable_base_address) ? _vtable_base_address : 0x20000000);
.vtable (_vtable_base_address) : AT (_vtable_base_address) {
KEEP (*(.vtable))
} > REGION_DATA
.descriptor :{
FILL(0x00000000);
. = ORIGIN(REGION_DESCRIPTOR) + LENGTH(REGION_DESCRIPTOR) - 1;
BYTE(0x00);
__ROM_AT = .;
} > REGION_DESCRIPTOR
.reset : {
KEEP(*(.reset))
} > REGION_RESET AT> REGION_RESET
.text : {
CREATE_OBJECT_SYMBOLS
KEEP (*(.text))
*(.text.*)
. = ALIGN(0x4);
KEEP (*(.ctors))
. = ALIGN(0x4);
KEEP (*(.dtors))
. = ALIGN(0x4);
__init_array_start = .;
KEEP (*(.init_array*))
__init_array_end = .;
KEEP (*(.init))
KEEP (*(.fini*))
} > REGION_TEXT AT> REGION_TEXT
.rodata : {
*(.rodata)
*(.rodata.*)
} > REGION_TEXT AT> REGION_TEXT
.ARM.exidx : {
__exidx_start = .;
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
__exidx_end = .;
} > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
.ARM.extab : {
KEEP (*(.ARM.extab* .gnu.linkonce.armextab.*))
} > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
__etext = .;
.data : {
__data_load__ = LOADADDR (.data);
__data_start__ = .;
KEEP (*(.data))
KEEP (*(.data*))
. = ALIGN (4);
__data_end__ = .;
} > REGION_DATA AT> REGION_TEXT
.bss : {
__bss_start__ = .;
*(.shbss)
KEEP (*(.bss))
*(.bss.*)
*(COMMON)
. = ALIGN (4);
__bss_end__ = .;
} > REGION_BSS AT> REGION_BSS
.heap : {
__heap_start__ = .;
end = __heap_start__;
_end = end;
__end = end;
KEEP (*(.heap))
__heap_end__ = .;
__HeapLimit = __heap_end__;
} > REGION_HEAP AT> REGION_HEAP
.stack (NOLOAD) : ALIGN(0x8) {
_stack = .;
KEEP(*(.stack))
} > REGION_STACK AT> REGION_STACK
__stack_top = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK);
PROVIDE(__stack = __stack_top);
}

361
contrib/loaders/flash/msp432/msp432p411x_algo.inc Normal file
View File

@ -0,0 +1,361 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
0x00,0x22,0x00,0x01,0x11,0x01,0x00,0x01,0x0d,0x12,0x00,0x01,0x0d,0x12,0x00,0x01,
0x0d,0x12,0x00,0x01,0x0d,0x12,0x00,0x01,0x0d,0x12,0x00,0x01,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x12,0x00,0x01,
0x0d,0x12,0x00,0x01,0x00,0x00,0x00,0x00,0x0d,0x12,0x00,0x01,0x0d,0x12,0x00,0x01,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x41,0xf2,0x00,0x70,0xc0,0xf2,0x00,0x10,0x85,0x46,0x05,0x48,0x05,0x49,0x4f,0xf0,
0x00,0x02,0x88,0x42,0xb8,0xbf,0x40,0xf8,0x04,0x2b,0xfa,0xdb,0x00,0xf0,0xaa,0xbf,
0x78,0x16,0x00,0x01,0x94,0x16,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x04,0x4b,0x05,0x48,0x1b,0x1a,0x06,0x2b,0x02,0xd9,0x04,0x4b,0x03,0xb1,0x18,0x47,
0x70,0x47,0x00,0xbf,0x37,0x24,0x00,0x20,0x34,0x24,0x00,0x20,0x00,0x00,0x00,0x00,
0x05,0x49,0x06,0x48,0x09,0x1a,0x89,0x10,0x01,0xeb,0xd1,0x71,0x49,0x10,0x02,0xd0,
0x03,0x4b,0x03,0xb1,0x18,0x47,0x70,0x47,0x34,0x24,0x00,0x20,0x34,0x24,0x00,0x20,
0x00,0x00,0x00,0x00,0x10,0xb5,0x06,0x4c,0x23,0x78,0x43,0xb9,0xff,0xf7,0xd8,0xff,
0x04,0x4b,0x13,0xb1,0x04,0x48,0xaf,0xf3,0x00,0x80,0x01,0x23,0x23,0x70,0x10,0xbd,
0x78,0x16,0x00,0x01,0x00,0x00,0x00,0x00,0x3c,0x12,0x00,0x01,0x08,0xb5,0x08,0x4b,
0x1b,0xb1,0x08,0x48,0x08,0x49,0xaf,0xf3,0x00,0x80,0x08,0x48,0x03,0x68,0x13,0xb9,
0xbd,0xe8,0x08,0x40,0xcc,0xe7,0x06,0x4b,0x00,0x2b,0xf9,0xd0,0x98,0x47,0xf7,0xe7,
0x00,0x00,0x00,0x00,0x3c,0x12,0x00,0x01,0x7c,0x16,0x00,0x01,0x34,0x24,0x00,0x20,
0x00,0x00,0x00,0x00,0x13,0x4b,0x00,0x2b,0x08,0xbf,0x11,0x4b,0x9d,0x46,0xa3,0xf5,
0x80,0x3a,0x00,0x21,0x8b,0x46,0x0f,0x46,0x11,0x48,0x12,0x4a,0x12,0x1a,0x00,0xf0,
0x79,0xf8,0x0d,0x4b,0x00,0x2b,0x00,0xd0,0x98,0x47,0x0c,0x4b,0x00,0x2b,0x00,0xd0,
0x98,0x47,0x00,0x20,0x00,0x21,0x04,0x00,0x0d,0x00,0x0b,0x48,0x00,0xf0,0x16,0xf8,
0x00,0xf0,0x40,0xf8,0x20,0x00,0x29,0x00,0x00,0xf0,0x04,0xff,0x00,0xf0,0x14,0xf8,
0x00,0x00,0x08,0x00,0x00,0x22,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x78,0x16,0x00,0x01,0x94,0x16,0x00,0x01,0xc9,0x02,0x00,0x01,0x01,0x46,0x00,0x20,
0x02,0x46,0x03,0x46,0x00,0xf0,0x9c,0xb8,0x08,0xb5,0x00,0x21,0x04,0x46,0x00,0xf0,
0xf3,0xf8,0x04,0x4b,0x18,0x68,0xc3,0x6b,0x03,0xb1,0x98,0x47,0x20,0x46,0x00,0xf0,
0x55,0xf9,0x00,0xbf,0x38,0x12,0x00,0x01,0x38,0xb5,0x08,0x4b,0x08,0x4d,0xed,0x1a,
0xac,0x10,0x18,0xbf,0xed,0x18,0x05,0xd0,0x01,0x3c,0x55,0xf8,0x04,0x3d,0x98,0x47,
0x00,0x2c,0xf9,0xd1,0xbd,0xe8,0x38,0x40,0x00,0xf0,0x9c,0xbf,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x70,0xb5,0x0f,0x4e,0x0f,0x4d,0x76,0x1b,0xb6,0x10,0x18,0xbf,
0x00,0x24,0x05,0xd0,0x01,0x34,0x55,0xf8,0x04,0x3b,0x98,0x47,0xa6,0x42,0xf9,0xd1,
0x0a,0x4e,0x0b,0x4d,0x76,0x1b,0x00,0xf0,0x7f,0xff,0xb6,0x10,0x18,0xbf,0x00,0x24,
0x06,0xd0,0x01,0x34,0x55,0xf8,0x04,0x3b,0x98,0x47,0xa6,0x42,0xf9,0xd1,0x70,0xbd,
0x70,0xbd,0x00,0xbf,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x12,0x00,0x01,
0x10,0x12,0x00,0x01,0x70,0xb4,0x84,0x07,0x46,0xd0,0x54,0x1e,0x00,0x2a,0x41,0xd0,
0xcd,0xb2,0x03,0x46,0x02,0xe0,0x62,0x1e,0xe4,0xb3,0x14,0x46,0x03,0xf8,0x01,0x5b,
0x9a,0x07,0xf8,0xd1,0x03,0x2c,0x2e,0xd9,0xcd,0xb2,0x45,0xea,0x05,0x25,0x0f,0x2c,
0x45,0xea,0x05,0x45,0x19,0xd9,0x03,0xf1,0x10,0x02,0x26,0x46,0x10,0x3e,0x0f,0x2e,
0x42,0xf8,0x10,0x5c,0x42,0xf8,0x0c,0x5c,0x42,0xf8,0x08,0x5c,0x42,0xf8,0x04,0x5c,
0x02,0xf1,0x10,0x02,0xf2,0xd8,0xa4,0xf1,0x10,0x02,0x22,0xf0,0x0f,0x02,0x04,0xf0,
0x0f,0x04,0x10,0x32,0x03,0x2c,0x13,0x44,0x0d,0xd9,0x1e,0x46,0x22,0x46,0x04,0x3a,
0x03,0x2a,0x46,0xf8,0x04,0x5b,0xfa,0xd8,0x22,0x1f,0x22,0xf0,0x03,0x02,0x04,0x32,
0x13,0x44,0x04,0xf0,0x03,0x04,0x2c,0xb1,0xc9,0xb2,0x1c,0x44,0x03,0xf8,0x01,0x1b,
0xa3,0x42,0xfb,0xd1,0x70,0xbc,0x70,0x47,0x14,0x46,0x03,0x46,0xc2,0xe7,0x00,0xbf,
0x2d,0xe9,0xf0,0x47,0x25,0x4c,0x25,0x68,0xd5,0xf8,0x48,0x41,0x06,0x46,0x88,0x46,
0x92,0x46,0x99,0x46,0xcc,0xb3,0x60,0x68,0x1f,0x28,0x18,0xdc,0x43,0x1c,0x7e,0xb1,
0x04,0xeb,0x80,0x05,0x01,0x21,0xc5,0xf8,0x88,0xa0,0xd4,0xf8,0x88,0x71,0x01,0xfa,
0x00,0xf2,0x17,0x43,0x02,0x2e,0xc4,0xf8,0x88,0x71,0xc5,0xf8,0x08,0x91,0x1e,0xd0,
0x02,0x30,0x63,0x60,0x44,0xf8,0x20,0x80,0x00,0x20,0xbd,0xe8,0xf0,0x87,0x14,0x4b,
0x03,0xb3,0x4f,0xf4,0xc8,0x70,0xaf,0xf3,0x00,0x80,0x04,0x46,0xd0,0xb1,0xd5,0xf8,
0x48,0x31,0x00,0x27,0x80,0xe8,0x88,0x00,0xc5,0xf8,0x48,0x41,0x38,0x46,0x01,0x23,
0xc4,0xf8,0x88,0x71,0xc4,0xf8,0x8c,0x71,0x00,0x2e,0xe1,0xd0,0xd0,0xe7,0xd4,0xf8,
0x8c,0x11,0x0a,0x43,0xc4,0xf8,0x8c,0x21,0xda,0xe7,0x05,0xf5,0xa6,0x74,0xc5,0xf8,
0x48,0x41,0xc0,0xe7,0x4f,0xf0,0xff,0x30,0xbd,0xe8,0xf0,0x87,0x38,0x12,0x00,0x01,
0x00,0x00,0x00,0x00,0x02,0x4b,0x13,0xb1,0x02,0x48,0xff,0xf7,0x07,0xbf,0x70,0x47,
0x00,0x00,0x00,0x00,0xc9,0x02,0x00,0x01,0x2d,0xe9,0xf0,0x4f,0x31,0x4b,0x83,0xb0,
0x1b,0x68,0x00,0x93,0x03,0xf5,0xa4,0x73,0x81,0x46,0x0e,0x46,0x01,0x93,0x00,0x9b,
0xd3,0xf8,0x48,0x71,0x27,0xb3,0xdd,0xf8,0x04,0xa0,0x7c,0x68,0x65,0x1e,0x0e,0xd4,
0x01,0x34,0x07,0xeb,0x84,0x04,0x4f,0xf0,0x00,0x08,0xe6,0xb1,0xd4,0xf8,0x00,0x31,
0xb3,0x42,0x18,0xd0,0x01,0x3d,0x6b,0x1c,0xa4,0xf1,0x04,0x04,0xf5,0xd1,0x22,0x4b,
0x73,0xb1,0x7b,0x68,0x00,0x2b,0x36,0xd1,0x3b,0x68,0x00,0x2b,0x34,0xd0,0x38,0x46,
0xca,0xf8,0x00,0x30,0xaf,0xf3,0x00,0x80,0xda,0xf8,0x00,0x70,0x00,0x2f,0xdc,0xd1,
0x03,0xb0,0xbd,0xe8,0xf0,0x8f,0x7b,0x68,0x22,0x68,0x01,0x3b,0xab,0x42,0x0c,0xbf,
0x7d,0x60,0xc4,0xf8,0x00,0x80,0x00,0x2a,0xdc,0xd0,0xd7,0xf8,0x88,0x31,0xd7,0xf8,
0x04,0xb0,0x01,0x21,0xa9,0x40,0x19,0x42,0x08,0xd1,0x90,0x47,0x7b,0x68,0x5b,0x45,
0xbd,0xd1,0xda,0xf8,0x00,0x30,0xbb,0x42,0xcc,0xd0,0xb8,0xe7,0xd7,0xf8,0x8c,0x31,
0x19,0x42,0x04,0xd1,0x48,0x46,0xd4,0xf8,0x80,0x10,0x90,0x47,0xee,0xe7,0xd4,0xf8,
0x80,0x00,0x90,0x47,0xea,0xe7,0x3b,0x68,0xba,0x46,0x1f,0x46,0x00,0x2f,0xac,0xd1,
0xce,0xe7,0x00,0xbf,0x38,0x12,0x00,0x01,0x00,0x00,0x00,0x00,0xfe,0xe7,0x00,0xbf,
0x4f,0x4a,0x13,0x68,0xc3,0xf3,0x05,0x23,0x04,0x3b,0xdb,0xb2,0x15,0x2b,0x70,0xb4,
0x00,0xf2,0x8c,0x80,0x01,0x22,0x02,0xfa,0x03,0xf3,0x13,0xf0,0x30,0x1f,0x61,0xd0,
0x02,0x23,0x98,0x42,0x31,0xd0,0x46,0x4b,0x1b,0x68,0xc3,0xf3,0x05,0x23,0x44,0x4c,
0x44,0x49,0x01,0x25,0x22,0x68,0x09,0x2b,0x10,0xd8,0xdf,0xe8,0x03,0xf0,0x05,0x35,
0x0f,0x0f,0x45,0x29,0x0f,0x0f,0x45,0x29,0x01,0x28,0x63,0xd0,0x02,0x28,0x73,0xd1,
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0xff,0x02,0x00,0x2b,0xfa,0xd1,0x23,0x68,0xc3,0xf3,0x05,0x23,0x04,0x3b,0xdb,0xb2,
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0x30,0x40,0xff,0xf7,0x35,0xbd,0x15,0x28,0x67,0xd0,0x18,0x28,0x5f,0xd0,0x14,0x28,
0xe5,0xd1,0x00,0x20,0xff,0xf7,0xda,0xfd,0x00,0x28,0xe0,0xd0,0x01,0x20,0xff,0xf7,
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0xa1,0xd0,0x02,0x20,0xba,0xe7,0x00,0x20,0xff,0xf7,0xa0,0xfd,0x00,0x28,0xa6,0xd0,
0x00,0x20,0xff,0xf7,0xed,0xfc,0x00,0x28,0xc5,0xd1,0xa0,0xe7,0x01,0x20,0xff,0xf7,
0x95,0xfd,0x00,0x28,0x8f,0xd0,0xec,0xe7,0x1e,0x4b,0x1b,0x78,0x00,0x2b,0x96,0xd1,
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0xe1,0xff,0x63,0x68,0x68,0x73,0x03,0xf4,0xe0,0x23,0xab,0x60,0x00,0x20,0xff,0xf7,
0xef,0xfe,0x33,0x68,0x02,0x21,0x5b,0x6d,0x05,0x46,0x00,0x20,0x98,0x47,0x33,0x68,
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0x23,0xf4,0xe0,0x23,0x43,0xf4,0x80,0x23,0x00,0x22,0x63,0x60,0x22,0x60,0x08,0x4b,
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0x6c,0x08,0x00,0x02,0x00,0xed,0x00,0xe0,0x80,0x01,0x00,0x20,0x00,0x04,0x01,0x40,
0x50,0x01,0x00,0x20,0x00,0xad,0xde,0x00,0x19,0x4b,0xdb,0x69,0xda,0x07,0x70,0xb5,
0x1d,0xd4,0x17,0x4c,0xe3,0x69,0x9b,0x07,0x00,0xd4,0x70,0xbd,0x15,0x4d,0x16,0x49,
0x2b,0x68,0x4f,0xf4,0x00,0x10,0x1b,0x69,0x98,0x47,0x23,0x6a,0x0b,0x2b,0x19,0xd0,
0x12,0x4b,0x10,0x4a,0x1b,0x68,0x12,0x68,0x9b,0x6c,0x14,0x69,0x98,0x47,0x10,0x49,
0x23,0x46,0x01,0x44,0xbd,0xe8,0x70,0x40,0x4f,0xf4,0x01,0x10,0x18,0x47,0x0b,0x4b,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x08,0x20,0x00,0x20,

122
contrib/loaders/flash/msp432/startup_msp432e4.c Normal file
View File

@ -0,0 +1,122 @@
/******************************************************************************
*
* Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
/* Entry point for the application. */
extern int main();
/* Reserve space for the system stack. */
extern uint32_t __stack_top;
typedef void(*pFunc)(void);
/* Interrupt handler prototypes */
void default_handler(void);
void reset_handler(void);
/*
* The vector table. Note that the proper constructs must be placed on this to
* ensure that it ends up at physical address 0x0000.0000 or at the start of
* the program if located at a start address other than 0.
*/
void (* const intr_vectors[])(void) __attribute__((section(".intvecs"))) = {
(pFunc)&__stack_top, /* The initial stack pointer */
reset_handler, /* The reset handler */
default_handler, /* The NMI handler */
default_handler, /* The hard fault handler */
default_handler, /* The MPU fault handler */
default_handler, /* The bus fault handler */
default_handler, /* The usage fault handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
default_handler, /* SVCall handler */
default_handler, /* Debug monitor handler */
0, /* Reserved */
default_handler, /* The PendSV handler */
default_handler /* The SysTick handler */
};
/*
* The following are constructs created by the linker, indicating where the
* the "data" and "bss" segments reside in memory. The initializers for the
* for the "data" segment resides immediately following the "text" segment.
*/
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
/*
* This is the code that gets called when the processor first starts execution
* following a reset event. Only the absolutely necessary set is performed,
* after which the application supplied entry() routine is called. Any fancy
* actions (such as making decisions based on the reset cause register, and
* resetting the bits in that register) are left solely in the hands of the
* application.
*/
__attribute__((section(".reset"))) __attribute__((naked))
void reset_handler(void)
{
/* Set stack pointer */
__asm(" MOVW.W r0, #0x1700\n"
" MOVT.W r0, #0x2000\n"
" mov sp, r0\n");
/* Zero fill the bss segment. */
__asm(" ldr r0, =__bss_start__\n"
" ldr r1, =__bss_end__\n"
" mov r2, #0\n"
" .thumb_func\n"
"zero_loop:\n"
" cmp r0, r1\n"
" it lt\n"
" strlt r2, [r0], #4\n"
" blt zero_loop");
/* Call the application's entry point. */
main();
}
/*
* This is the code that gets called when the processor receives an unexpected
* interrupt. This simply enters an infinite loop, preserving the system state
* for examination by a debugger.
*/
void default_handler(void)
{
/* Enter an infinite loop. */
while (1)
;
}

122
contrib/loaders/flash/msp432/startup_msp432p4.c Normal file
View File

@ -0,0 +1,122 @@
/******************************************************************************
*
* Copyright (C) 2012-2018 Texas Instruments Incorporated - http://www.ti.com/
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************/
#include <stdint.h>
/* Entry point for the application. */
extern int main();
/* Reserve space for the system stack. */
extern uint32_t __stack_top;
typedef void(*pFunc)(void);
/* Interrupt handler prototypes */
void default_handler(void);
void reset_handler(void);
/*
* The vector table. Note that the proper constructs must be placed on this to
* ensure that it ends up at physical address 0x0000.0000 or at the start of
* the program if located at a start address other than 0.
*/
void (* const intr_vectors[])(void) __attribute__((section(".intvecs"))) = {
(pFunc)&__stack_top, /* The initial stack pointer */
reset_handler, /* The reset handler */
default_handler, /* The NMI handler */
default_handler, /* The hard fault handler */
default_handler, /* The MPU fault handler */
default_handler, /* The bus fault handler */
default_handler, /* The usage fault handler */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
0, /* Reserved */
default_handler, /* SVCall handler */
default_handler, /* Debug monitor handler */
0, /* Reserved */
default_handler, /* The PendSV handler */
default_handler /* The SysTick handler */
};
/*
* The following are constructs created by the linker, indicating where the
* the "data" and "bss" segments reside in memory. The initializers for the
* for the "data" segment resides immediately following the "text" segment.
*/
extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
/*
* This is the code that gets called when the processor first starts execution
* following a reset event. Only the absolutely necessary set is performed,
* after which the application supplied entry() routine is called. Any fancy
* actions (such as making decisions based on the reset cause register, and
* resetting the bits in that register) are left solely in the hands of the
* application.
*/
__attribute__((section(".reset"))) __attribute__((naked))
void reset_handler(void)
{
/* Set stack pointer */
__asm(" MOVW.W r0, #0x1700\n"
" MOVT.W r0, #0x0100\n"
" mov sp, r0\n");
/* Zero fill the bss segment. */
__asm(" ldr r0, =__bss_start__\n"
" ldr r1, =__bss_end__\n"
" mov r2, #0\n"
" .thumb_func\n"
"zero_loop:\n"
" cmp r0, r1\n"
" it lt\n"
" strlt r2, [r0], #4\n"
" blt zero_loop");
/* Call the application's entry point. */
main();
}
/*
* This is the code that gets called when the processor receives an unexpected
* interrupt. This simply enters an infinite loop, preserving the system state
* for examination by a debugger.
*/
void default_handler(void)
{
/* Enter an infinite loop. */
while (1)
;
}

35
doc/openocd.texi
View File

@ -6000,6 +6000,41 @@ if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
@end example @end example
@end deffn @end deffn
@deffn {Flash Driver} msp432
All versions of the SimpleLink MSP432 microcontrollers from Texas
Instruments include internal flash. The msp432 flash driver automatically
recognizes the specific version's flash parameters and autoconfigures itself.
Main program flash (starting at address 0) is flash bank 0. Information flash
region on MSP432P4 versions (starting at address 0x200000) is flash bank 1.
@example
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
@end example
@deffn Command {msp432 mass_erase} [main|all]
Performs a complete erase of flash. By default, @command{mass_erase} will erase
only the main program flash.
On MSP432P4 versions, using @command{mass_erase all} will erase both the
main program and information flash regions. To also erase the BSL in information
flash, the user must first use the @command{bsl} command.
@end deffn
@deffn Command {msp432 bsl} [unlock|lock]
On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
region in information flash so that flash commands can erase or write the BSL.
Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
To erase and program the BSL:
@example
msp432 bsl unlock
flash erase_address 0x202000 0x2000
flash write_image bsl.bin 0x202000
msp432 bsl lock
@end example
@end deffn
@end deffn
@deffn {Flash Driver} niietcm4 @deffn {Flash Driver} niietcm4
This drivers handles the integrated NOR flash on NIIET Cortex-M4 This drivers handles the integrated NOR flash on NIIET Cortex-M4
based controllers. Flash size and sector layout are auto-configured by the driver. based controllers. Flash size and sector layout are auto-configured by the driver.

4
src/flash/nor/Makefile.am
View File

@ -36,6 +36,7 @@ NOR_DRIVERS = \
%D%/lpc2900.c \ %D%/lpc2900.c \
%D%/lpcspifi.c \ %D%/lpcspifi.c \
%D%/mdr.c \ %D%/mdr.c \
%D%/msp432.c \
%D%/mrvlqspi.c \ %D%/mrvlqspi.c \
%D%/niietcm4.c \ %D%/niietcm4.c \
%D%/non_cfi.c \ %D%/non_cfi.c \
@ -73,4 +74,5 @@ NORHEADERS = \
%D%/imp.h \ %D%/imp.h \
%D%/non_cfi.h \ %D%/non_cfi.h \
%D%/ocl.h \ %D%/ocl.h \
%D%/spi.h %D%/spi.h \
%D%/msp432.h

2
src/flash/nor/drivers.c
View File

@ -50,6 +50,7 @@ extern struct flash_driver lpc2900_flash;
extern struct flash_driver lpcspifi_flash; extern struct flash_driver lpcspifi_flash;
extern struct flash_driver mdr_flash; extern struct flash_driver mdr_flash;
extern struct flash_driver mrvlqspi_flash; extern struct flash_driver mrvlqspi_flash;
extern struct flash_driver msp432_flash;
extern struct flash_driver niietcm4_flash; extern struct flash_driver niietcm4_flash;
extern struct flash_driver nrf5_flash; extern struct flash_driver nrf5_flash;
extern struct flash_driver nrf51_flash; extern struct flash_driver nrf51_flash;
@ -113,6 +114,7 @@ static struct flash_driver *flash_drivers[] = {
&lpcspifi_flash, &lpcspifi_flash,
&mdr_flash, &mdr_flash,
&mrvlqspi_flash, &mrvlqspi_flash,
&msp432_flash,
&niietcm4_flash, &niietcm4_flash,
&nrf5_flash, &nrf5_flash,
&nrf51_flash, &nrf51_flash,

1103
src/flash/nor/msp432.c Normal file
View File

File diff suppressed because it is too large Load Diff

127
src/flash/nor/msp432.h Normal file
View File

@ -0,0 +1,127 @@
/***************************************************************************
* Copyright (C) 2018 by Texas Instruments, Inc. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_FLASH_NOR_MSP432_H
#define OPENOCD_FLASH_NOR_MSP432_H
/* MSP432 family types */
#define MSP432_NO_FAMILY 0 /* Family type not determined yet */
#define MSP432E4 1 /* MSP432E4 family of devices */
#define MSP432P4 2 /* MSP432P4 family of devices */
/* MSP432 device types */
#define MSP432_NO_TYPE 0 /* Device type not determined yet */
#define MSP432P401X_DEPR 1 /* Early MSP432P401x offerings, now deprecated */
#define MSP432P401X 2 /* MSP432P401x device, revision C or higher */
#define MSP432P411X 3 /* MSP432P411x device, revision A or higher */
#define MSP432P401X_GUESS 4 /* Assuming it's an MSP432P401x device */
#define MSP432P411X_GUESS 5 /* Assuming it's an MSP432P411x device */
#define MSP432E401Y 6 /* MSP432E401Y device */
#define MSP432E411Y 7 /* MSP432E401Y device */
#define MSP432E4X_GUESS 8 /* Assuming it's an MSP432E4x device */
/* MSP432P4 flash parameters */
#define P4_FLASH_MAIN_BASE 0x00000000
#define P4_FLASH_INFO_BASE 0x00200000
#define P4_SECTOR_LENGTH 0x1000
#define P4_ALGO_ENTRY_ADDR 0x01000110
/* MSP432E4 flash paramters */
#define E4_FLASH_BASE 0x00000000
#define E4_FLASH_SIZE 0x100000
#define E4_SECTOR_LENGTH 0x4000
#define E4_ALGO_ENTRY_ADDR 0x20000110
/* Flash helper algorithm key addresses */
#define ALGO_BASE_ADDR 0x20000000
#define ALGO_BUFFER1_ADDR 0x20002000
#define ALGO_BUFFER2_ADDR 0x20003000
#define ALGO_PARAMS_BASE_ADDR 0x20000150
#define ALGO_FLASH_COMMAND_ADDR 0x20000150
#define ALGO_RETURN_CODE_ADDR 0x20000154
#define ALGO_FLASH_DEST_ADDR 0x2000015c
#define ALGO_FLASH_LENGTH_ADDR 0x20000160
#define ALGO_BUFFER1_STATUS_ADDR 0x20000164
#define ALGO_BUFFER2_STATUS_ADDR 0x20000168
#define ALGO_ERASE_PARAM_ADDR 0x2000016c
#define ALGO_UNLOCK_BSL_ADDR 0x20000170
#define ALGO_STACK_POINTER_ADDR 0x20002000
/* Flash helper algorithm key sizes */
#define ALGO_BUFFER_SIZE 0x1000
#define ALGO_WORKING_SIZE (ALGO_BUFFER2_ADDR + 0x1000 - ALGO_BASE_ADDR)
/* Flash helper algorithm flash commands */
#define FLASH_NO_COMMAND 0
#define FLASH_MASS_ERASE 1
#define FLASH_SECTOR_ERASE 2
#define FLASH_PROGRAM 4
#define FLASH_INIT 8
#define FLASH_EXIT 16
#define FLASH_CONTINUOUS 32
/* Flash helper algorithm return codes */
#define FLASH_BUSY 0x00000001
#define FLASH_SUCCESS 0x00000ACE
#define FLASH_ERROR 0x0000DEAD
#define FLASH_TIMEOUT_ERROR 0xDEAD0000
#define FLASH_VERIFY_ERROR 0xDEADDEAD
#define FLASH_WRONG_COMMAND 0x00000BAD
#define FLASH_POWER_ERROR 0x00DEAD00
/* Flash helper algorithm buffer status values */
#define BUFFER_INACTIVE 0x00
#define BUFFER_ACTIVE 0x01
#define BUFFER_DATA_READY 0x10
/* Flash helper algorithm erase parameters */
#define FLASH_ERASE_MAIN 0x01
#define FLASH_ERASE_INFO 0x02
/* Flash helper algorithm lock/unlock BSL options */
#define FLASH_LOCK_BSL 0x00
#define FLASH_UNLOCK_BSL 0x0b
/* Flash helper algorithm parameter block struct */
struct msp432_algo_params {
uint8_t flash_command[4];
uint8_t return_code[4];
uint8_t _reserved0[4];
uint8_t address[4];
uint8_t length[4];
uint8_t buffer1_status[4];
uint8_t buffer2_status[4];
uint8_t erase_param[4];
uint8_t unlock_bsl[4];
};
/* Flash helper algorithm for MSP432P401x targets */
const uint8_t msp432p401x_algo[] = {
#include "../../../contrib/loaders/flash/msp432/msp432p401x_algo.inc"
};
/* Flash helper algorithm for MSP432P411x targets */
const uint8_t msp432p411x_algo[] = {
#include "../../../contrib/loaders/flash/msp432/msp432p411x_algo.inc"
};
/* Flash helper algorithm for MSP432E4x targets */
const uint8_t msp432e4x_algo[] = {
#include "../../../contrib/loaders/flash/msp432/msp432e4x_algo.inc"
};
#endif /* OPENOCD_FLASH_NOR_MSP432_H */

7
tcl/board/ti_msp432_launchpad.cfg Normal file
View File

@ -0,0 +1,7 @@
#
# TI MSP432 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
adapter_khz 2500
transport select swd
source [find target/ti_msp432.cfg]

18
tcl/target/ti_msp432p4xx.cfg → tcl/target/ti_msp432.cfg
View File

@ -1,5 +1,5 @@
# #
# Texas Instruments MSP432P4xx - ARM Cortex-M4F @ up to 48 MHz # Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz
# #
# http://www.ti.com/MSP432 # http://www.ti.com/MSP432
# #
@ -7,7 +7,7 @@
if { [info exists CHIPNAME] } { if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME set _CHIPNAME $CHIPNAME
} else { } else {
set _CHIPNAME msp432p4xx set _CHIPNAME msp432
} }
if { [info exists CPUTAPID] } { if { [info exists CPUTAPID] } {
@ -39,15 +39,13 @@ target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if { [info exists WORKAREASIZE] } { if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE set _WORKAREASIZE $WORKAREASIZE
} else { } else {
# On MSP432P401x Bank0 (8k) is always powered set _WORKAREASIZE 0x4000
set _WORKAREASIZE 0x2000
} }
$_TARGETNAME configure -work-area-phys 0x20000000 \ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-work-area-size $_WORKAREASIZE -work-area-backup 0
if { ![using_hla] } { set _FLASHNAME $_CHIPNAME.flash
cortex_m reset_config sysresetreq flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
}
adapter_khz 500 reset_config srst_only
adapter_nsrst_delay 100