Tim Newsome
GitHub
commit
3ddbbd525d
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@ -433,8 +433,8 @@ static void increase_dmi_busy_delay(struct target *target)
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* exec: If this is set, assume the scan results in an execution, so more
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* run-test/idle cycles may be required.
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*/
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static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
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uint32_t *data_in, dmi_op_t op, uint16_t address_out, uint32_t data_out,
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static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
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uint32_t *data_in, dmi_op_t op, uint32_t address_out, uint32_t data_out,
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bool exec)
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{
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riscv013_info_t *info = get_info(target);
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@ -479,12 +479,12 @@ static dmi_status_t dmi_scan(struct target *target, uint16_t *address_in,
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return buf_get_u32(in, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH);
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}
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static uint32_t dmi_read(struct target *target, uint16_t address)
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static int dmi_read(struct target *target, uint32_t *value, uint32_t address)
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{
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select_dmi(target);
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dmi_status_t status;
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uint16_t address_in;
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uint32_t address_in;
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unsigned i = 0;
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@ -500,21 +500,20 @@ static uint32_t dmi_read(struct target *target, uint16_t address)
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break;
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} else {
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LOG_ERROR("failed read from 0x%x, status=%d", address, status);
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break;
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return ERROR_FAIL;
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}
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}
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("Failed read from 0x%x; status=%d", address, status);
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return ~0;
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return ERROR_FAIL;
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}
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/* This second loop ensures that we got the read
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* data back. Note that NOP can result in a 'busy' result as well, but
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* that would be noticed on the next DMI access we do. */
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uint32_t value;
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for (i = 0; i < 256; i++) {
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status = dmi_scan(target, &address_in, &value, DMI_OP_NOP, address, 0,
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status = dmi_scan(target, &address_in, value, DMI_OP_NOP, address, 0,
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false);
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if (status == DMI_STATUS_BUSY) {
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increase_dmi_busy_delay(target);
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@ -522,7 +521,7 @@ static uint32_t dmi_read(struct target *target, uint16_t address)
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break;
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} else {
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LOG_ERROR("failed read (NOP) at 0x%x, status=%d", address, status);
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break;
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return ERROR_FAIL;
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}
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}
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@ -531,15 +530,15 @@ static uint32_t dmi_read(struct target *target, uint16_t address)
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LOG_ERROR("Failed read (NOP) from 0x%x; status=%d", address, status);
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} else {
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LOG_ERROR("Failed read (NOP) from 0x%x; value=0x%x, status=%d",
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address, value, status);
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address, *value, status);
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}
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return ~0;
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return ERROR_FAIL;
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}
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return value;
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return ERROR_OK;
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}
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static int dmi_write(struct target *target, uint16_t address, uint64_t value)
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static int dmi_write(struct target *target, uint32_t address, uint32_t value)
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{
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select_dmi(target);
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dmi_status_t status = DMI_STATUS_BUSY;
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@ -581,7 +580,7 @@ static int dmi_write(struct target *target, uint16_t address, uint64_t value)
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}
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}
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if (status != DMI_STATUS_SUCCESS) {
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LOG_ERROR("failed to write (NOP) 0x%" PRIx64 " to 0x%x; status=%d", value, address, status);
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LOG_ERROR("failed to write (NOP) 0x%x to 0x%x; status=%d", value, address, status);
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return ERROR_FAIL;
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}
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@ -591,7 +590,8 @@ static int dmi_write(struct target *target, uint16_t address, uint64_t value)
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int dmstatus_read(struct target *target, uint32_t *dmstatus,
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bool authenticated)
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{
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*dmstatus = dmi_read(target, DMI_DMSTATUS);
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if (dmi_read(target, dmstatus, DMI_DMSTATUS) != ERROR_OK)
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return ERROR_FAIL;
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if (authenticated && !get_field(*dmstatus, DMI_DMSTATUS_AUTHENTICATED)) {
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LOG_ERROR("Debugger is not authenticated to target Debug Module. "
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"(dmstatus=0x%x). Use `riscv authdata_read` and "
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@ -632,7 +632,8 @@ static int wait_for_idle(struct target *target, uint32_t *abstractcs)
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RISCV013_INFO(info);
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time_t start = time(NULL);
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while (1) {
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*abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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if (dmi_read(target, abstractcs, DMI_ABSTRACTCS) != ERROR_OK)
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return ERROR_FAIL;
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if (get_field(*abstractcs, DMI_ABSTRACTCS_BUSY) == 0)
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return ERROR_OK;
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@ -674,7 +675,9 @@ static int execute_abstract_command(struct target *target, uint32_t command)
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wait_for_idle(target, &abstractcs);
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}
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uint32_t cs = dmi_read(target, DMI_ABSTRACTCS);
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uint32_t cs;
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if (dmi_read(target, &cs, DMI_ABSTRACTCS) != ERROR_OK)
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return ERROR_FAIL;
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info->cmderr = get_field(cs, DMI_ABSTRACTCS_CMDERR);
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if (info->cmderr != 0) {
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LOG_DEBUG("command 0x%x failed; abstractcs=0x%x", command, cs);
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@ -691,16 +694,19 @@ static riscv_reg_t read_abstract_arg(struct target *target, unsigned index,
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unsigned size_bits)
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{
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riscv_reg_t value = 0;
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uint32_t v;
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unsigned offset = index * size_bits / 32;
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switch (size_bits) {
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default:
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LOG_ERROR("Unsupported size: %d", size_bits);
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return ~0;
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case 64:
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value |= ((uint64_t) dmi_read(target, DMI_DATA0 + offset + 1)) << 32;
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dmi_read(target, &v, DMI_DATA0 + offset + 1);
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value |= ((uint64_t) v) << 32;
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/* falls through */
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case 32:
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value |= dmi_read(target, DMI_DATA0 + offset);
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dmi_read(target, &v, DMI_DATA0 + offset);
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value |= v;
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}
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return value;
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}
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@ -871,7 +877,9 @@ static int examine_progbuf(struct target *target)
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return ERROR_OK;
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}
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uint32_t written = dmi_read(target, DMI_PROGBUF0);
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uint32_t written;
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if (dmi_read(target, &written, DMI_PROGBUF0) != ERROR_OK)
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return ERROR_FAIL;
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if (written == (uint32_t) info->progbuf_address) {
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LOG_INFO("progbuf is writable at 0x%" PRIx64,
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info->progbuf_address);
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@ -961,16 +969,23 @@ static int scratch_find(struct target *target,
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static int scratch_read64(struct target *target, scratch_mem_t *scratch,
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uint64_t *value)
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{
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uint32_t v;
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switch (scratch->memory_space) {
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case SPACE_DMI_DATA:
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*value = dmi_read(target, DMI_DATA0 + scratch->debug_address);
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*value |= ((uint64_t) dmi_read(target, DMI_DATA1 +
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scratch->debug_address)) << 32;
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if (dmi_read(target, &v, DMI_DATA0 + scratch->debug_address) != ERROR_OK)
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return ERROR_FAIL;
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*value = v;
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if (dmi_read(target, &v, DMI_DATA1 + scratch->debug_address) != ERROR_OK)
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return ERROR_FAIL;
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*value |= ((uint64_t) v) << 32;
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break;
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case SPACE_DMI_PROGBUF:
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*value = dmi_read(target, DMI_PROGBUF0 + scratch->debug_address);
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*value |= ((uint64_t) dmi_read(target, DMI_PROGBUF1 +
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scratch->debug_address)) << 32;
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if (dmi_read(target, &v, DMI_PROGBUF0 + scratch->debug_address) != ERROR_OK)
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return ERROR_FAIL;
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*value = v;
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if (dmi_read(target, &v, DMI_PROGBUF1 + scratch->debug_address) != ERROR_OK)
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return ERROR_FAIL;
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*value |= ((uint64_t) v) << 32;
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break;
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case SPACE_DMI_RAM:
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{
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@ -1269,7 +1284,9 @@ static int examine(struct target *target)
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uint32_t max_hartsel_mask = ((1L<<10)-1) << DMI_DMCONTROL_HARTSEL_OFFSET;
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dmi_write(target, DMI_DMCONTROL, max_hartsel_mask | DMI_DMCONTROL_DMACTIVE);
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uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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uint32_t dmcontrol;
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if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
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return ERROR_FAIL;
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if (!get_field(dmcontrol, DMI_DMCONTROL_DMACTIVE)) {
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LOG_ERROR("Debug Module did not become active. dmcontrol=0x%x",
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@ -1285,7 +1302,9 @@ static int examine(struct target *target)
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}
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LOG_DEBUG("hartsellen=%d", info->hartsellen);
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uint32_t hartinfo = dmi_read(target, DMI_HARTINFO);
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uint32_t hartinfo;
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if (dmi_read(target, &hartinfo, DMI_HARTINFO) != ERROR_OK)
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return ERROR_FAIL;
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info->datasize = get_field(hartinfo, DMI_HARTINFO_DATASIZE);
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info->dataaccess = get_field(hartinfo, DMI_HARTINFO_DATAACCESS);
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@ -1302,10 +1321,13 @@ static int examine(struct target *target)
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return ERROR_OK;
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}
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info->sbcs = dmi_read(target, DMI_SBCS);
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if (dmi_read(target, &info->sbcs, DMI_SBCS) != ERROR_OK)
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return ERROR_FAIL;
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/* Check that abstract data registers are accessible. */
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uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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uint32_t abstractcs;
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if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK)
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return ERROR_FAIL;
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info->datacount = get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT);
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info->progbufsize = get_field(abstractcs, DMI_ABSTRACTCS_PROGBUFSIZE);
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@ -1412,8 +1434,7 @@ int riscv013_authdata_read(struct target *target, uint32_t *value)
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if (wait_for_authbusy(target, NULL) != ERROR_OK)
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return ERROR_FAIL;
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*value = dmi_read(target, DMI_AUTHDATA);
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return ERROR_OK;
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return dmi_read(target, value, DMI_AUTHDATA);
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}
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int riscv013_authdata_write(struct target *target, uint32_t value)
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@ -1469,6 +1490,8 @@ static int init_target(struct command_context *cmd_ctx,
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generic_info->dmi_write_u64_bits = &riscv013_dmi_write_u64_bits;
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generic_info->authdata_read = &riscv013_authdata_read;
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generic_info->authdata_write = &riscv013_authdata_write;
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generic_info->dmi_read = &dmi_read;
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generic_info->dmi_write = &dmi_write;
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generic_info->version_specific = calloc(1, sizeof(riscv013_info_t));
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if (!generic_info->version_specific)
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return ERROR_FAIL;
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@ -1533,7 +1556,9 @@ static int assert_reset(struct target *target)
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dmi_write(target, DMI_DMCONTROL, control);
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/* Read back to check if hartreset is supported. */
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uint32_t rb = dmi_read(target, DMI_DMCONTROL);
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uint32_t rb;
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if (dmi_read(target, &rb, DMI_DMCONTROL) != ERROR_OK)
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return ERROR_FAIL;
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if (!get_field(rb, DMI_DMCONTROL_HARTRESET)) {
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/* Use ndmreset instead. That will reset the entire device, but
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* that's probably what OpenOCD wants anyway. */
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@ -1668,21 +1693,25 @@ static int read_memory_bus_word(struct target *target, target_addr_t address,
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{
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uint32_t value;
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if (size > 12) {
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value = dmi_read(target, DMI_SBDATA3);
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if (dmi_read(target, &value, DMI_SBDATA3) != ERROR_OK)
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return ERROR_FAIL;
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write_to_buf(buffer + 12, value, 4);
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log_memory_access(address + 12, value, 4, true);
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}
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if (size > 8) {
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value = dmi_read(target, DMI_SBDATA2);
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if (dmi_read(target, &value, DMI_SBDATA2) != ERROR_OK)
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return ERROR_FAIL;
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write_to_buf(buffer + 8, value, 4);
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log_memory_access(address + 8, value, 4, true);
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}
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if (size > 4) {
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value = dmi_read(target, DMI_SBDATA1);
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if (dmi_read(target, &value, DMI_SBDATA1) != ERROR_OK)
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return ERROR_FAIL;
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write_to_buf(buffer + 4, value, 4);
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log_memory_access(address + 4, value, 4, true);
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}
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value = dmi_read(target, DMI_SBDATA0);
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if (dmi_read(target, &value, DMI_SBDATA0) != ERROR_OK)
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return ERROR_FAIL;
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write_to_buf(buffer, value, MIN(size, 4));
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log_memory_access(address, value, MIN(size, 4), true);
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return ERROR_OK;
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@ -1711,13 +1740,16 @@ static target_addr_t sb_read_address(struct target *target)
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RISCV013_INFO(info);
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unsigned sbasize = get_field(info->sbcs, DMI_SBCS_SBASIZE);
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target_addr_t address = 0;
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uint32_t v;
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if (sbasize > 32) {
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#if BUILD_TARGET64
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address |= dmi_read(target, DMI_SBADDRESS1);
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dmi_read(target, &v, DMI_SBADDRESS1);
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address |= v;
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address <<= 32;
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#endif
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}
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address |= dmi_read(target, DMI_SBADDRESS0);
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dmi_read(target, &v, DMI_SBADDRESS0);
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address |= v;
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return address;
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}
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@ -1746,7 +1778,8 @@ static int read_sbcs_nonbusy(struct target *target, uint32_t *sbcs)
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{
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time_t start = time(NULL);
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while (1) {
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*sbcs = dmi_read(target, DMI_SBCS);
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if (dmi_read(target, sbcs, DMI_SBCS) != ERROR_OK)
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return ERROR_FAIL;
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if (!get_field(*sbcs, DMI_SBCS_SBBUSY))
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return ERROR_OK;
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if (time(NULL) - start > riscv_command_timeout_sec) {
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@ -1924,9 +1957,12 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
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/* Wait for the target to finish performing the last abstract command,
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* and update our copy of cmderr. */
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uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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uint32_t abstractcs;
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if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK)
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return ERROR_FAIL;
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while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
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abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK)
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return ERROR_FAIL;
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info->cmderr = get_field(abstractcs, DMI_ABSTRACTCS_CMDERR);
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unsigned cmderr = info->cmderr;
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@ -1975,7 +2011,10 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
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/* This is definitely a good version of the value that we
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* attempted to read when we discovered that the target was
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* busy. */
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dmi_data0 = dmi_read(target, DMI_DATA0);
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if (dmi_read(target, &dmi_data0, DMI_DATA0) != ERROR_OK) {
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riscv_batch_free(batch);
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goto error;
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}
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/* Clobbers DMI_DATA0. */
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result = register_read_direct(target, &next_read_addr,
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@ -2035,7 +2074,9 @@ static int read_memory_progbuf(struct target *target, target_addr_t address,
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if (count > 1) {
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/* Read the penultimate word. */
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uint64_t value = dmi_read(target, DMI_DATA0);
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uint32_t value;
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if (dmi_read(target, &value, DMI_DATA0) != ERROR_OK)
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goto error;
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write_to_buf(buffer + receive_addr - address, value, size);
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log_memory_access(receive_addr, value, size, true);
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receive_addr += size;
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@ -2292,9 +2333,12 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
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* is this read to abstractcs that will cause the dmi_busy_delay
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* to be incremented if necessary. */
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uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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uint32_t abstractcs;
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if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK)
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goto error;
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while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY))
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abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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if (dmi_read(target, &abstractcs, DMI_ABSTRACTCS) != ERROR_OK)
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return ERROR_FAIL;
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info->cmderr = get_field(abstractcs, DMI_ABSTRACTCS_CMDERR);
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switch (info->cmderr) {
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case CMDERR_NONE:
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@ -2440,7 +2484,8 @@ static void riscv013_select_current_hart(struct target *target)
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{
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RISCV_INFO(r);
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uint64_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
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uint32_t dmcontrol;
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dmi_read(target, &dmcontrol, DMI_DMCONTROL);
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dmcontrol = set_field(dmcontrol, hartsel_mask(target), r->current_hartid);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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}
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@ -2453,7 +2498,9 @@ static int riscv013_halt_current_hart(struct target *target)
|
|||
LOG_ERROR("Hart %d is already halted!", r->current_hartid);
|
||||
|
||||
/* Issue the halt command, and then wait for the current hart to halt. */
|
||||
uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
|
||||
uint32_t dmcontrol;
|
||||
if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_HALTREQ, 1);
|
||||
dmi_write(target, DMI_DMCONTROL, dmcontrol);
|
||||
for (size_t i = 0; i < 256; ++i)
|
||||
|
|
@ -2464,7 +2511,8 @@ static int riscv013_halt_current_hart(struct target *target)
|
|||
uint32_t dmstatus;
|
||||
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
dmcontrol = dmi_read(target, DMI_DMCONTROL);
|
||||
if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
|
||||
LOG_ERROR("unable to halt hart %d", r->current_hartid);
|
||||
LOG_ERROR(" dmcontrol=0x%08x", dmcontrol);
|
||||
|
|
@ -2546,7 +2594,9 @@ int riscv013_write_debug_buffer(struct target *target, unsigned index, riscv_ins
|
|||
|
||||
riscv_insn_t riscv013_read_debug_buffer(struct target *target, unsigned index)
|
||||
{
|
||||
return dmi_read(target, DMI_PROGBUF0 + index);
|
||||
uint32_t value;
|
||||
dmi_read(target, &value, DMI_PROGBUF0 + index);
|
||||
return value;
|
||||
}
|
||||
|
||||
int riscv013_execute_debug_buffer(struct target *target)
|
||||
|
|
@ -2638,7 +2688,9 @@ static int riscv013_step_or_resume_current_hart(struct target *target, bool step
|
|||
return ERROR_FAIL;
|
||||
|
||||
/* Issue the resume command, and then wait for the current hart to resume. */
|
||||
uint32_t dmcontrol = dmi_read(target, DMI_DMCONTROL);
|
||||
uint32_t dmcontrol;
|
||||
if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 1);
|
||||
dmi_write(target, DMI_DMCONTROL, dmcontrol);
|
||||
|
||||
|
|
@ -2659,7 +2711,8 @@ static int riscv013_step_or_resume_current_hart(struct target *target, bool step
|
|||
|
||||
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
dmcontrol = dmi_read(target, DMI_DMCONTROL);
|
||||
if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
LOG_ERROR("unable to resume hart %d", r->current_hartid);
|
||||
LOG_ERROR(" dmcontrol=0x%08x", dmcontrol);
|
||||
LOG_ERROR(" dmstatus =0x%08x", dmstatus);
|
||||
|
|
@ -2677,9 +2730,10 @@ void riscv013_clear_abstract_error(struct target *target)
|
|||
{
|
||||
/* Wait for busy to go away. */
|
||||
time_t start = time(NULL);
|
||||
uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
|
||||
uint32_t abstractcs;
|
||||
dmi_read(target, &abstractcs, DMI_ABSTRACTCS);
|
||||
while (get_field(abstractcs, DMI_ABSTRACTCS_BUSY)) {
|
||||
abstractcs = dmi_read(target, DMI_ABSTRACTCS);
|
||||
dmi_read(target, &abstractcs, DMI_ABSTRACTCS);
|
||||
|
||||
if (time(NULL) - start > riscv_command_timeout_sec) {
|
||||
LOG_ERROR("abstractcs.busy is not going low after %d seconds "
|
||||
|
|
|
|||
|
|
@ -1361,6 +1361,61 @@ COMMAND_HANDLER(riscv_authdata_write)
|
|||
}
|
||||
}
|
||||
|
||||
COMMAND_HANDLER(riscv_dmi_read)
|
||||
{
|
||||
if (CMD_ARGC != 1) {
|
||||
LOG_ERROR("Command takes 1 parameter");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
struct target *target = get_current_target(CMD_CTX);
|
||||
if (!target) {
|
||||
LOG_ERROR("target is NULL!");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
RISCV_INFO(r);
|
||||
if (!r) {
|
||||
LOG_ERROR("riscv_info is NULL!");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (r->dmi_read) {
|
||||
uint32_t address, value;
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
|
||||
if (r->dmi_read(target, &value, address) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
command_print(CMD_CTX, "0x%" PRIx32, value);
|
||||
return ERROR_OK;
|
||||
} else {
|
||||
LOG_ERROR("dmi_read is not implemented for this target.");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
COMMAND_HANDLER(riscv_dmi_write)
|
||||
{
|
||||
if (CMD_ARGC != 2) {
|
||||
LOG_ERROR("Command takes exactly 2 arguments");
|
||||
return ERROR_COMMAND_SYNTAX_ERROR;
|
||||
}
|
||||
|
||||
struct target *target = get_current_target(CMD_CTX);
|
||||
RISCV_INFO(r);
|
||||
|
||||
uint32_t address, value;
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
|
||||
|
||||
if (r->dmi_write) {
|
||||
return r->dmi_write(target, address, value);
|
||||
} else {
|
||||
LOG_ERROR("dmi_write is not implemented for this target.");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct command_registration riscv_exec_command_handlers[] = {
|
||||
{
|
||||
.name = "set_command_timeout_sec",
|
||||
|
|
@ -1406,6 +1461,20 @@ static const struct command_registration riscv_exec_command_handlers[] = {
|
|||
.usage = "riscv authdata_write value",
|
||||
.help = "Write the 32-bit value to authdata."
|
||||
},
|
||||
{
|
||||
.name = "dmi_read",
|
||||
.handler = riscv_dmi_read,
|
||||
.mode = COMMAND_ANY,
|
||||
.usage = "riscv dmi_read address",
|
||||
.help = "Perform a 32-bit DMI read at address, returning the value."
|
||||
},
|
||||
{
|
||||
.name = "dmi_write",
|
||||
.handler = riscv_dmi_write,
|
||||
.mode = COMMAND_ANY,
|
||||
.usage = "riscv dmi_write address value",
|
||||
.help = "Perform a 32-bit DMI write of value at address."
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -113,6 +113,9 @@ typedef struct {
|
|||
|
||||
int (*authdata_read)(struct target *target, uint32_t *value);
|
||||
int (*authdata_write)(struct target *target, uint32_t value);
|
||||
|
||||
int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
|
||||
int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
|
||||
} riscv_info_t;
|
||||
|
||||
/* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue