dsp5680xx - indent fix
no logic changes, only coding style (spaces to tabs, etc) Change-Id: I5933447c633990e103bc62d088ca2e12f11f031d Signed-off-by: rodrigo_l_rosa <rodrigorosa.lg@gmail.com> Reviewed-on: http://openocd.zylin.com/253 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>__archive__
rodrigo_l_rosa
Øyvind Harboe
parent
b7ce3b5d15
commit
3d0e2547fe
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@ -35,14 +35,10 @@
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*
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#ifndef DSP5680XX_FLASH_H
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#define DSP5680XX_FLASH_H
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#include "imp.h"
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#include <helper/binarybuffer.h>
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#include <helper/time_support.h>
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@ -53,10 +49,13 @@ struct dsp5680xx_flash_bank {
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struct working_area *write_algorithm;
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};
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static int dsp5680xx_build_sector_list(struct flash_bank *bank){
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static int dsp5680xx_build_sector_list(struct flash_bank *bank)
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{
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uint32_t offset = HFM_FLASH_BASE_ADDR;
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bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
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int i;
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for (i = 0; i < bank->num_sectors; ++i) {
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bank->sectors[i].offset = i * HFM_SECTOR_SIZE;
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bank->sectors[i].size = HFM_SECTOR_SIZE;
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@ -64,19 +63,20 @@ static int dsp5680xx_build_sector_list(struct flash_bank *bank){
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bank->sectors[i].is_erased = -1;
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bank->sectors[i].is_protected = -1;
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}
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LOG_USER("%s not tested yet.",__FUNCTION__);
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LOG_USER("%s not tested yet.", __func__);
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return ERROR_OK;
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}
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// flash bank dsp5680xx 0 0 0 0 <target#>
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FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command){
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/* flash bank dsp5680xx 0 0 0 0 <target#> */
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FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command)
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{
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struct dsp5680xx_flash_bank *nbank;
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nbank = malloc(sizeof(struct dsp5680xx_flash_bank));
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bank->base = HFM_FLASH_BASE_ADDR;
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bank->size = HFM_SIZE_BYTES; // top 4k not accessible
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bank->size = HFM_SIZE_BYTES; /* top 4k not accessible */
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bank->driver_priv = nbank;
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bank->num_sectors = HFM_SECTOR_COUNT;
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dsp5680xx_build_sector_list(bank);
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@ -93,9 +93,12 @@ FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command){
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*
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* @return
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*/
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static int dsp5680xx_flash_protect_check(struct flash_bank *bank){
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static int dsp5680xx_flash_protect_check(struct flash_bank *bank)
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{
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int retval = ERROR_OK;
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uint16_t protected = 0;
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retval = dsp5680xx_f_protect_check(bank->target, &protected);
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if (retval != ERROR_OK) {
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for (int i = 0; i < HFM_SECTOR_COUNT; i++)
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@ -127,9 +130,15 @@ static int dsp5680xx_flash_protect_check(struct flash_bank *bank){
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*
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* @return
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*/
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static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first, int last){
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// This applies security to flash module after next reset, it does not actually apply protection (protection refers to undesired access from the core)
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static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first,
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int last)
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{
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/**
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* This applies security to flash module after next reset, it does
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* not actually apply protection (protection refers to undesired access from the core)
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*/
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int retval;
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if (set)
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retval = dsp5680xx_f_lock(bank->target);
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else {
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@ -154,34 +163,54 @@ else{
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*
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* @return
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*/
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static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count){
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static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t * buffer,
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uint32_t offset, uint32_t count)
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{
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int retval;
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if ((offset + count / 2) > bank->size) {
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LOG_ERROR("%s: Flash bank cannot fit data.",__FUNCTION__);
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LOG_ERROR("%s: Flash bank cannot fit data.", __func__);
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return ERROR_FAIL;
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}
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if (offset % 2) {
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LOG_ERROR("%s: Writing to odd addresses not supported. This chip uses word addressing, Openocd only supports byte addressing. The workaround results in disabling writing to odd byte addresses.",__FUNCTION__);
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/**
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* Writing to odd addresses not supported.
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* This chip uses word addressing, Openocd only supports byte addressing.
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* The workaround results in disabling writing to odd byte addresses
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*/
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LOG_ERROR
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("%s: Writing to odd addresses not supported for this target",
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__func__);
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return ERROR_FAIL;
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}
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retval = dsp5680xx_f_wr(bank->target, buffer, bank->base + offset/2, count, 0);
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retval =
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dsp5680xx_f_wr(bank->target, buffer, bank->base + offset / 2, count,
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0);
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uint32_t addr_word;
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for(addr_word = bank->base + offset/2;addr_word<count/2;addr_word+=(HFM_SECTOR_SIZE/2)){
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for (addr_word = bank->base + offset / 2; addr_word < count / 2;
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addr_word += (HFM_SECTOR_SIZE / 2)) {
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if (retval == ERROR_OK)
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bank->sectors[addr_word/(HFM_SECTOR_SIZE/2)].is_erased = 0;
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bank->sectors[addr_word /
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(HFM_SECTOR_SIZE / 2)].is_erased = 0;
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else
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bank->sectors[addr_word/(HFM_SECTOR_SIZE/2)].is_erased = -1;
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bank->sectors[addr_word /
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(HFM_SECTOR_SIZE / 2)].is_erased = -1;
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}
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return retval;
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}
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static int dsp5680xx_probe(struct flash_bank *bank){
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LOG_DEBUG("%s not implemented",__FUNCTION__);
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static int dsp5680xx_probe(struct flash_bank *bank)
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{
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LOG_DEBUG("%s not implemented", __func__);
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return ERROR_OK;
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}
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static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf, int buf_size){
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snprintf(buf, buf_size, "\ndsp5680xx flash driver info:\n - Currently only full erase/lock/unlock are implemented. \n - Call with bank==0 and sector 0 to 0.\n - Protect requires arp_init-reset to complete. \n - Before removing protection the master tap must be selected, and arp_init-reset is required to complete unlocking.");
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static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf,
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int buf_size)
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{
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snprintf(buf, buf_size,
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"\ndsp5680xx flash driver info:\n - See comments in code.");
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return ERROR_OK;
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}
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@ -195,16 +224,23 @@ static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf, int buf_size
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*
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* @return
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*/
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static int dsp5680xx_flash_erase(struct flash_bank * bank, int first, int last){
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static int dsp5680xx_flash_erase(struct flash_bank *bank, int first, int last)
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{
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int retval;
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retval = dsp5680xx_f_erase(bank->target, (uint32_t) first, (uint32_t) last);
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if ((!(first|last)) || ((first == 0) && (last == (HFM_SECTOR_COUNT-1))))
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retval =
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dsp5680xx_f_erase(bank->target, (uint32_t) first, (uint32_t) last);
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if ((!(first | last))
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|| ((first == 0) && (last == (HFM_SECTOR_COUNT - 1))))
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last = HFM_SECTOR_COUNT - 1;
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if (retval == ERROR_OK)
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for (int i = first; i <= last; i++)
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bank->sectors[i].is_erased = 1;
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else
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// If an error occurred unknown status is set even though some sector could have been correctly erased.
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/**
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* If an error occurred unknown status
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*is set even though some sector could have been correctly erased.
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*/
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for (int i = first; i <= last; i++)
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bank->sectors[i].is_erased = -1;
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return retval;
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@ -218,13 +254,18 @@ if ((!(first|last)) || ((first == 0) && (last == (HFM_SECTOR_COUNT-1))))
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*
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* @return
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*/
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static int dsp5680xx_flash_erase_check(struct flash_bank * bank){
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static int dsp5680xx_flash_erase_check(struct flash_bank *bank)
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{
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int retval = ERROR_OK;
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uint8_t erased = 0;
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uint32_t i;
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for (i = 0; i < HFM_SECTOR_COUNT; i++) {
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if (bank->sectors[i].is_erased == -1) {
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retval = dsp5680xx_f_erase_check(bank->target,&erased,i);
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retval =
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dsp5680xx_f_erase_check(bank->target, &erased, i);
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if (retval != ERROR_OK) {
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bank->sectors[i].is_erased = -1;
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} else {
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@ -244,11 +285,10 @@ struct flash_driver dsp5680xx_flash = {
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.erase = dsp5680xx_flash_erase,
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.protect = dsp5680xx_flash_protect,
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.write = dsp5680xx_flash_write,
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//.read = default_flash_read,
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/* .read = default_flash_read, */
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.probe = dsp5680xx_probe,
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.auto_probe = dsp5680xx_probe,
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.erase_check = dsp5680xx_flash_erase_check,
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.protect_check = dsp5680xx_flash_protect_check,
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.info = dsp5680xx_flash_info
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};
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#endif // dsp5680xx_flash.h
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File diff suppressed because it is too large
Load Diff
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@ -37,13 +37,13 @@
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*
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*/
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#define S_FILE_DATA_OFFSET 0x200000
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#define TIME_DIV_FREESCALE 0.3
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//----------------------------------------------------------------
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// JTAG
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* JTAG
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*----------------------------------------------------------------
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*/
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#define DSP5680XX_JTAG_CORE_TAP_IRLEN 4
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#define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8
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@ -64,21 +64,26 @@
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#define JTAG_INSTR_ENABLE_ONCE 0x6
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#define JTAG_INSTR_DEBUG_REQUEST 0x7
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#define JTAG_INSTR_BYPASS 0xF
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// Master TAP instructions from MC56F8000RM.pdf
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* Master TAP instructions from MC56F8000RM.pdf
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* ----------------------------------------------------------------
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*/
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#define MASTER_TAP_CMD_BYPASS 0xF
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#define MASTER_TAP_CMD_IDCODE 0x2
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#define MASTER_TAP_CMD_TLM_SEL 0x5
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#define MASTER_TAP_CMD_FLASH_ERASE 0x8
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// EOnCE control register info
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* EOnCE control register info
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_OCR_EX (1<<5)
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/* EX Bit Definition
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0 Remain in the Debug Processing State
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@ -88,35 +93,43 @@
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0 Inactive—No Action Taken
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1 Execute Controller Instruction */
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#define DSP5680XX_ONCE_OCR_RW (1<<7)
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/* RW Bit Definition
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0 Write To the Register Specified by the RS[4:0] Bits
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1 ReadFrom the Register Specified by the RS[4:0] Bits */
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//----------------------------------------------------------------
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/** RW Bit Definition
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* 0 Write To the Register Specified by the RS[4:0] Bits
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* 1 ReadFrom the Register Specified by the RS[4:0] Bits
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// EOnCE Status Register
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* EOnCE Status Register
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_OSCR_OS1 (1<<5)
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#define DSP5680XX_ONCE_OSCR_OS0 (1<<4)
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// EOnCE Core Status - Describes the operating status of the core controller
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* EOnCE Core Status - Describes the operating status of the core controller
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_OSCR_NORMAL_M (0)
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//00 - Normal - Controller Core Executing Instructions or in Reset
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/* 00 - Normal - Controller Core Executing Instructions or in Reset */
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#define DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0)
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//01 - Stop/Wait - Controller Core in Stop or Wait Mode
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/* 01 - Stop/Wait - Controller Core in Stop or Wait Mode */
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#define DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1)
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//10 - Busy - Controller is Performing External or Peripheral Access (Wait States)
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/* 10 - Busy - Controller is Performing External or Peripheral Access (Wait States) */
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#define DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)
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//11 - Debug - Controller Core Halted and in Debug Mode
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/* 11 - Debug - Controller Core Halted and in Debug Mode */
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#define EONCE_STAT_MASK 0x30
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
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* ----------------------------------------------------------------
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*/
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#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
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#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
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#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
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@ -136,41 +149,52 @@
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#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
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#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
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#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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#define FLUSH_COUNT_READ_WRITE 8192 // This value works, higher values (and lower...) may work as well.
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#define FLUSH_COUNT_FLASH 8192
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//----------------------------------------------------------------
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// HFM (flash module) Commands (ref:MC56F801xRM.pdf@159)
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//----------------------------------------------------------------
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/** ----------------------------------------------------------------
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* HFM (flash module) Commands (ref:MC56F801xRM.pdf@159)
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* ----------------------------------------------------------------
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*/
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#define HFM_ERASE_VERIFY 0x05
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#define HFM_CALCULATE_DATA_SIGNATURE 0x06
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#define HFM_WORD_PROGRAM 0x20
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#define HFM_PAGE_ERASE 0x40
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#define HFM_MASS_ERASE 0x41
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#define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66
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//----------------------------------------------------------------
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/**
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* ----------------------------------------------------------------
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*/
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//----------------------------------------------------------------
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// Flashing (ref:MC56F801xRM.pdf@159)
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//----------------------------------------------------------------
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#define HFM_BASE_ADDR 0x0F400 // In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR to get data into x: mem.)
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// The following are register addresses, not memory addresses (though all registers are memory mapped)
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#define HFM_CLK_DIV 0x00 // r/w
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#define HFM_CNFG 0x01 // r/w
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#define HFM_SECHI 0x03 // r
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#define HFM_SECLO 0x04 // r
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#define HFM_PROT 0x10 // r/w
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#define HFM_PROTB 0x11 // r/w
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#define HFM_USTAT 0x13 // r/w
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#define HFM_CMD 0x14 // r/w
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#define HFM_DATA 0x18 // r
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#define HFM_OPT1 0x1B // r
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#define HFM_TSTSIG 0x1D // r
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/** ----------------------------------------------------------------
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* Flashing (ref:MC56F801xRM.pdf@159)
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* ----------------------------------------------------------------
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*/
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#define HFM_BASE_ADDR 0x0F400 /** In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR
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* to get data into x: mem.)
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*/
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/**
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* The following are register addresses, not memory
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* addresses (though all registers are memory mapped)
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*/
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#define HFM_CLK_DIV 0x00 /* r/w */
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#define HFM_CNFG 0x01 /* r/w */
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#define HFM_SECHI 0x03 /* r */
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#define HFM_SECLO 0x04 /* r */
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#define HFM_PROT 0x10 /* r/w */
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#define HFM_PROTB 0x11 /* r/w */
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#define HFM_USTAT 0x13 /* r/w */
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#define HFM_CMD 0x14 /* r/w */
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#define HFM_DATA 0x18 /* r */
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#define HFM_OPT1 0x1B /* r */
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#define HFM_TSTSIG 0x1D /* r */
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#define HFM_EXEC_COMPLETE 0x40
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// User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5)
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/* User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5) */
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#define HFM_USTAT_MASK_BLANK 0x4
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#define HFM_USTAT_MASK_PVIOL_ACCER 0x30
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@ -182,11 +206,11 @@
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#define HFM_CLK_DEFAULT 0x27
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/* 0x27 according to freescale cfg, but 0x40 according to freescale spreadsheet... */
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#define HFM_FLASH_BASE_ADDR 0x0
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#define HFM_SIZE_BYTES 0x4000 // bytes
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||||
#define HFM_SIZE_WORDS 0x2000 // words
|
||||
#define HFM_SECTOR_SIZE 0x200 // Size in bytes
|
||||
#define HFM_SIZE_BYTES 0x4000 /* bytes */
|
||||
#define HFM_SIZE_WORDS 0x2000 /* words */
|
||||
#define HFM_SECTOR_SIZE 0x200 /* Size in bytes */
|
||||
#define HFM_SECTOR_COUNT 0x20
|
||||
// A 16K block in pages of 256 words.
|
||||
/* A 16K block in pages of 256 words. */
|
||||
|
||||
/**
|
||||
* Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.
|
||||
|
|
@ -194,26 +218,34 @@
|
|||
#define HFM_LOCK_FLASH 0xE70A
|
||||
#define HFM_LOCK_ADDR_L 0x1FF7
|
||||
#define HFM_LOCK_ADDR_H 0x1FF8
|
||||
//----------------------------------------------------------------
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// Register Memory Map (eonce_rev.1.0_0208081.pdf@16)
|
||||
//----------------------------------------------------------------
|
||||
/** ----------------------------------------------------------------
|
||||
* Register Memory Map (eonce_rev.1.0_0208081.pdf@16)
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define MC568013_EONCE_OBASE_ADDR 0xFF
|
||||
// The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...)
|
||||
#define MC568013_EONCE_TX_RX_ADDR 0xFFFE //
|
||||
#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR
|
||||
#define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR
|
||||
//----------------------------------------------------------------
|
||||
/* The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) */
|
||||
#define MC568013_EONCE_TX_RX_ADDR 0xFFFE
|
||||
#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF /* Relative to EONCE_OBASE_ADDR */
|
||||
#define MC568013_EONCE_OCR 0xFFA0 /* Relative to EONCE_OBASE_ADDR */
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
//----------------------------------------------------------------
|
||||
// SIM addresses & commands (MC56F80xx.h from freescale)
|
||||
//----------------------------------------------------------------
|
||||
/** ----------------------------------------------------------------
|
||||
* SIM addresses & commands (MC56F80xx.h from freescale)
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
#define MC568013_SIM_BASE_ADDR 0xF140
|
||||
#define MC56803x_2x_SIM_BASE_ADDR 0xF100
|
||||
|
||||
#define SIM_CMD_RESET 0x10
|
||||
//----------------------------------------------------------------
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
*/
|
||||
|
||||
/**
|
||||
* ----------------------------------------------------------------
|
||||
|
|
@ -254,7 +286,6 @@
|
|||
*/
|
||||
|
||||
struct dsp5680xx_common {
|
||||
//TODO
|
||||
uint32_t stored_pc;
|
||||
int flush;
|
||||
bool debug_mode_enabled;
|
||||
|
|
@ -262,7 +293,9 @@ bool debug_mode_enabled;
|
|||
|
||||
extern struct dsp5680xx_common dsp5680xx_context;
|
||||
|
||||
static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target){
|
||||
static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target
|
||||
*target)
|
||||
{
|
||||
return target->arch_info;
|
||||
}
|
||||
|
||||
|
|
@ -279,7 +312,8 @@ static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock);
|
||||
int dsp5680xx_f_wr(struct target *target, uint8_t * buffer, uint32_t address,
|
||||
uint32_t count, int is_flash_lock);
|
||||
|
||||
/**
|
||||
* The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis.
|
||||
|
|
@ -290,7 +324,8 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
|
|||
*
|
||||
* @return
|
||||
*/
|
||||
int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased, uint32_t sector);
|
||||
int dsp5680xx_f_erase_check(struct target *target, uint8_t * erased,
|
||||
uint32_t sector);
|
||||
|
||||
/**
|
||||
* Erases either a sector or the complete flash array. If either the range first-last covers the complete array or if @first == 0 and @last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased.
|
||||
|
|
@ -333,4 +368,4 @@ int dsp5680xx_f_lock(struct target * target);
|
|||
*/
|
||||
int dsp5680xx_f_unlock(struct target *target);
|
||||
|
||||
#endif // dsp5680xx.h
|
||||
#endif /* dsp5680xx.h */
|
||||
|
|
|
|||
Loading…
Reference in New Issue