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dsp5680xx - indent fix 

no logic changes, only coding style (spaces to tabs, etc)

Change-Id: I5933447c633990e103bc62d088ca2e12f11f031d
Signed-off-by: rodrigo_l_rosa <rodrigorosa.lg@gmail.com>
Reviewed-on: http://openocd.zylin.com/253
Tested-by: jenkins
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
__archive__
rodrigo_l_rosa 2011-12-05 11:22:27 -08:00 committed by Øyvind Harboe
parent b7ce3b5d15
commit 3d0e2547fe
3 changed files with 2412 additions and 1930 deletions
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296
src/flash/nor/dsp5680xx_flash.c
View File

@ -35,14 +35,10 @@
* *
*/ */
#ifdef HAVE_CONFIG_H #ifdef HAVE_CONFIG_H
#include "config.h" #include "config.h"
#endif #endif
#ifndef DSP5680XX_FLASH_H
#define DSP5680XX_FLASH_H
#include "imp.h" #include "imp.h"
#include <helper/binarybuffer.h> #include <helper/binarybuffer.h>
#include <helper/time_support.h> #include <helper/time_support.h>
@ -53,35 +49,39 @@ struct dsp5680xx_flash_bank {
struct working_area *write_algorithm; struct working_area *write_algorithm;
}; };
static int dsp5680xx_build_sector_list(struct flash_bank *bank){ static int dsp5680xx_build_sector_list(struct flash_bank *bank)
uint32_t offset = HFM_FLASH_BASE_ADDR; {
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors); uint32_t offset = HFM_FLASH_BASE_ADDR;
int i;
for (i = 0; i < bank->num_sectors; ++i){ bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
bank->sectors[i].offset = i*HFM_SECTOR_SIZE; int i;
bank->sectors[i].size = HFM_SECTOR_SIZE;
offset += bank->sectors[i].size; for (i = 0; i < bank->num_sectors; ++i) {
bank->sectors[i].is_erased = -1; bank->sectors[i].offset = i * HFM_SECTOR_SIZE;
bank->sectors[i].is_protected = -1; bank->sectors[i].size = HFM_SECTOR_SIZE;
} offset += bank->sectors[i].size;
LOG_USER("%s not tested yet.",__FUNCTION__); bank->sectors[i].is_erased = -1;
return ERROR_OK; bank->sectors[i].is_protected = -1;
}
LOG_USER("%s not tested yet.", __func__);
return ERROR_OK;
} }
// flash bank dsp5680xx 0 0 0 0 <target#> /* flash bank dsp5680xx 0 0 0 0 <target#> */
FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command){ FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command)
struct dsp5680xx_flash_bank *nbank; {
struct dsp5680xx_flash_bank *nbank;
nbank = malloc(sizeof(struct dsp5680xx_flash_bank)); nbank = malloc(sizeof(struct dsp5680xx_flash_bank));
bank->base = HFM_FLASH_BASE_ADDR; bank->base = HFM_FLASH_BASE_ADDR;
bank->size = HFM_SIZE_BYTES; // top 4k not accessible bank->size = HFM_SIZE_BYTES; /* top 4k not accessible */
bank->driver_priv = nbank; bank->driver_priv = nbank;
bank->num_sectors = HFM_SECTOR_COUNT; bank->num_sectors = HFM_SECTOR_COUNT;
dsp5680xx_build_sector_list(bank); dsp5680xx_build_sector_list(bank);
return ERROR_OK; return ERROR_OK;
} }
/** /**
@ -93,26 +93,29 @@ FLASH_BANK_COMMAND_HANDLER(dsp5680xx_flash_bank_command){
* *
* @return * @return
*/ */
static int dsp5680xx_flash_protect_check(struct flash_bank *bank){ static int dsp5680xx_flash_protect_check(struct flash_bank *bank)
int retval = ERROR_OK; {
uint16_t protected = 0; int retval = ERROR_OK;
retval = dsp5680xx_f_protect_check(bank->target,&protected);
if(retval != ERROR_OK){ uint16_t protected = 0;
for(int i = 0;i<HFM_SECTOR_COUNT;i++)
bank->sectors[i].is_protected = -1; retval = dsp5680xx_f_protect_check(bank->target, &protected);
return ERROR_OK; if (retval != ERROR_OK) {
} for (int i = 0; i < HFM_SECTOR_COUNT; i++)
for(int i = 0;i<HFM_SECTOR_COUNT/2;i++){ bank->sectors[i].is_protected = -1;
if(protected & 1){ return ERROR_OK;
bank->sectors[2*i].is_protected = 1; }
bank->sectors[2*i+1].is_protected = 1; for (int i = 0; i < HFM_SECTOR_COUNT / 2; i++) {
}else{ if (protected & 1) {
bank->sectors[2*i].is_protected = 0; bank->sectors[2 * i].is_protected = 1;
bank->sectors[2*i+1].is_protected = 0; bank->sectors[2 * i + 1].is_protected = 1;
} } else {
protected = (protected >> 1); bank->sectors[2 * i].is_protected = 0;
} bank->sectors[2 * i + 1].is_protected = 0;
return retval; }
protected = (protected >> 1);
}
return retval;
} }
/** /**
@ -127,21 +130,27 @@ static int dsp5680xx_flash_protect_check(struct flash_bank *bank){
* *
* @return * @return
*/ */
static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first, int last){ static int dsp5680xx_flash_protect(struct flash_bank *bank, int set, int first,
// This applies security to flash module after next reset, it does not actually apply protection (protection refers to undesired access from the core) int last)
int retval; {
if(set) /**
retval = dsp5680xx_f_lock(bank->target); * This applies security to flash module after next reset, it does
else{ * not actually apply protection (protection refers to undesired access from the core)
retval = dsp5680xx_f_unlock(bank->target); */
if (retval == ERROR_OK) { int retval;
/* mark all as erased */
for (int i = 0; i <= (HFM_SECTOR_COUNT-1); i++) if (set)
/* FM does not recognize it as erased if erased via JTAG. */ retval = dsp5680xx_f_lock(bank->target);
bank->sectors[i].is_erased = 1; else {
retval = dsp5680xx_f_unlock(bank->target);
if (retval == ERROR_OK) {
/* mark all as erased */
for (int i = 0; i <= (HFM_SECTOR_COUNT - 1); i++)
/* FM does not recognize it as erased if erased via JTAG. */
bank->sectors[i].is_erased = 1;
}
} }
} return retval;
return retval;
} }
/** /**
@ -154,34 +163,54 @@ else{
* *
* @return * @return
*/ */
static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count){ static int dsp5680xx_flash_write(struct flash_bank *bank, uint8_t * buffer,
int retval; uint32_t offset, uint32_t count)
if((offset + count/2)>bank->size){ {
LOG_ERROR("%s: Flash bank cannot fit data.",__FUNCTION__); int retval;
return ERROR_FAIL;
} if ((offset + count / 2) > bank->size) {
if(offset%2){ LOG_ERROR("%s: Flash bank cannot fit data.", __func__);
LOG_ERROR("%s: Writing to odd addresses not supported. This chip uses word addressing, Openocd only supports byte addressing. The workaround results in disabling writing to odd byte addresses.",__FUNCTION__); return ERROR_FAIL;
return ERROR_FAIL; }
} if (offset % 2) {
retval = dsp5680xx_f_wr(bank->target, buffer, bank->base + offset/2, count, 0); /**
uint32_t addr_word; * Writing to odd addresses not supported.
for(addr_word = bank->base + offset/2;addr_word<count/2;addr_word+=(HFM_SECTOR_SIZE/2)){ * This chip uses word addressing, Openocd only supports byte addressing.
if(retval == ERROR_OK) * The workaround results in disabling writing to odd byte addresses
bank->sectors[addr_word/(HFM_SECTOR_SIZE/2)].is_erased = 0; */
else LOG_ERROR
bank->sectors[addr_word/(HFM_SECTOR_SIZE/2)].is_erased = -1; ("%s: Writing to odd addresses not supported for this target",
} __func__);
return retval; return ERROR_FAIL;
}
retval =
dsp5680xx_f_wr(bank->target, buffer, bank->base + offset / 2, count,
0);
uint32_t addr_word;
for (addr_word = bank->base + offset / 2; addr_word < count / 2;
addr_word += (HFM_SECTOR_SIZE / 2)) {
if (retval == ERROR_OK)
bank->sectors[addr_word /
(HFM_SECTOR_SIZE / 2)].is_erased = 0;
else
bank->sectors[addr_word /
(HFM_SECTOR_SIZE / 2)].is_erased = -1;
}
return retval;
} }
static int dsp5680xx_probe(struct flash_bank *bank){ static int dsp5680xx_probe(struct flash_bank *bank)
LOG_DEBUG("%s not implemented",__FUNCTION__); {
return ERROR_OK; LOG_DEBUG("%s not implemented", __func__);
return ERROR_OK;
} }
static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf, int buf_size){ static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf,
snprintf(buf, buf_size, "\ndsp5680xx flash driver info:\n - Currently only full erase/lock/unlock are implemented. \n - Call with bank==0 and sector 0 to 0.\n - Protect requires arp_init-reset to complete. \n - Before removing protection the master tap must be selected, and arp_init-reset is required to complete unlocking."); int buf_size)
{
snprintf(buf, buf_size,
"\ndsp5680xx flash driver info:\n - See comments in code.");
return ERROR_OK; return ERROR_OK;
} }
@ -195,19 +224,26 @@ static int dsp5680xx_flash_info(struct flash_bank *bank, char *buf, int buf_size
* *
* @return * @return
*/ */
static int dsp5680xx_flash_erase(struct flash_bank * bank, int first, int last){ static int dsp5680xx_flash_erase(struct flash_bank *bank, int first, int last)
int retval; {
retval = dsp5680xx_f_erase(bank->target, (uint32_t) first, (uint32_t) last); int retval;
if ((!(first|last)) || ((first == 0) && (last == (HFM_SECTOR_COUNT-1))))
last = HFM_SECTOR_COUNT-1; retval =
if(retval == ERROR_OK) dsp5680xx_f_erase(bank->target, (uint32_t) first, (uint32_t) last);
for(int i = first;i<=last;i++) if ((!(first | last))
bank->sectors[i].is_erased = 1; || ((first == 0) && (last == (HFM_SECTOR_COUNT - 1))))
else last = HFM_SECTOR_COUNT - 1;
// If an error occurred unknown status is set even though some sector could have been correctly erased. if (retval == ERROR_OK)
for(int i = first;i<=last;i++) for (int i = first; i <= last; i++)
bank->sectors[i].is_erased = -1; bank->sectors[i].is_erased = 1;
return retval; else
/**
* If an error occurred unknown status
*is set even though some sector could have been correctly erased.
*/
for (int i = first; i <= last; i++)
bank->sectors[i].is_erased = -1;
return retval;
} }
/** /**
@ -218,37 +254,41 @@ if ((!(first|last)) || ((first == 0) && (last == (HFM_SECTOR_COUNT-1))))
* *
* @return * @return
*/ */
static int dsp5680xx_flash_erase_check(struct flash_bank * bank){ static int dsp5680xx_flash_erase_check(struct flash_bank *bank)
int retval = ERROR_OK; {
uint8_t erased = 0; int retval = ERROR_OK;
uint32_t i;
for(i=0;i<HFM_SECTOR_COUNT;i++){ uint8_t erased = 0;
if(bank->sectors[i].is_erased == -1){
retval = dsp5680xx_f_erase_check(bank->target,&erased,i); uint32_t i;
if (retval != ERROR_OK){
bank->sectors[i].is_erased = -1; for (i = 0; i < HFM_SECTOR_COUNT; i++) {
}else{ if (bank->sectors[i].is_erased == -1) {
if(erased) retval =
bank->sectors[i].is_erased = 1; dsp5680xx_f_erase_check(bank->target, &erased, i);
else if (retval != ERROR_OK) {
bank->sectors[i].is_erased = 0; bank->sectors[i].is_erased = -1;
} } else {
} if (erased)
} bank->sectors[i].is_erased = 1;
return retval; else
bank->sectors[i].is_erased = 0;
}
}
}
return retval;
} }
struct flash_driver dsp5680xx_flash = { struct flash_driver dsp5680xx_flash = {
.name = "dsp5680xx_flash", .name = "dsp5680xx_flash",
.flash_bank_command = dsp5680xx_flash_bank_command, .flash_bank_command = dsp5680xx_flash_bank_command,
.erase = dsp5680xx_flash_erase, .erase = dsp5680xx_flash_erase,
.protect = dsp5680xx_flash_protect, .protect = dsp5680xx_flash_protect,
.write = dsp5680xx_flash_write, .write = dsp5680xx_flash_write,
//.read = default_flash_read, /* .read = default_flash_read, */
.probe = dsp5680xx_probe, .probe = dsp5680xx_probe,
.auto_probe = dsp5680xx_probe, .auto_probe = dsp5680xx_probe,
.erase_check = dsp5680xx_flash_erase_check, .erase_check = dsp5680xx_flash_erase_check,
.protect_check = dsp5680xx_flash_protect_check, .protect_check = dsp5680xx_flash_protect_check,
.info = dsp5680xx_flash_info .info = dsp5680xx_flash_info
}; };
#endif // dsp5680xx_flash.h

3775
src/target/dsp5680xx.c
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File diff suppressed because it is too large Load Diff

271
src/target/dsp5680xx.h
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@ -37,140 +37,164 @@
* *
*/ */
#define S_FILE_DATA_OFFSET 0x200000 #define S_FILE_DATA_OFFSET 0x200000
#define TIME_DIV_FREESCALE 0.3 #define TIME_DIV_FREESCALE 0.3
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// JTAG * JTAG
//---------------------------------------------------------------- *----------------------------------------------------------------
*/
#define DSP5680XX_JTAG_CORE_TAP_IRLEN 4 #define DSP5680XX_JTAG_CORE_TAP_IRLEN 4
#define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8 #define DSP5680XX_JTAG_MASTER_TAP_IRLEN 8
#define JTAG_STATUS_MASK 0x0F #define JTAG_STATUS_MASK 0x0F
#define JTAG_STATUS_NORMAL 0x01 #define JTAG_STATUS_NORMAL 0x01
#define JTAG_STATUS_STOPWAIT 0x05 #define JTAG_STATUS_STOPWAIT 0x05
#define JTAG_STATUS_BUSY 0x09 #define JTAG_STATUS_BUSY 0x09
#define JTAG_STATUS_DEBUG 0x0D #define JTAG_STATUS_DEBUG 0x0D
#define JTAG_STATUS_DEAD 0x0f #define JTAG_STATUS_DEAD 0x0f
#define JTAG_INSTR_EXTEST 0x0 #define JTAG_INSTR_EXTEST 0x0
#define JTAG_INSTR_SAMPLE_PRELOAD 0x1 #define JTAG_INSTR_SAMPLE_PRELOAD 0x1
#define JTAG_INSTR_IDCODE 0x2 #define JTAG_INSTR_IDCODE 0x2
#define JTAG_INSTR_EXTEST_PULLUP 0x3 #define JTAG_INSTR_EXTEST_PULLUP 0x3
#define JTAG_INSTR_HIGHZ 0x4 #define JTAG_INSTR_HIGHZ 0x4
#define JTAG_INSTR_CLAMP 0x5 #define JTAG_INSTR_CLAMP 0x5
#define JTAG_INSTR_ENABLE_ONCE 0x6 #define JTAG_INSTR_ENABLE_ONCE 0x6
#define JTAG_INSTR_DEBUG_REQUEST 0x7 #define JTAG_INSTR_DEBUG_REQUEST 0x7
#define JTAG_INSTR_BYPASS 0xF #define JTAG_INSTR_BYPASS 0xF
//---------------------------------------------------------------- /**
* ----------------------------------------------------------------
*/
/** ----------------------------------------------------------------
//---------------------------------------------------------------- * Master TAP instructions from MC56F8000RM.pdf
// Master TAP instructions from MC56F8000RM.pdf * ----------------------------------------------------------------
//---------------------------------------------------------------- */
#define MASTER_TAP_CMD_BYPASS 0xF #define MASTER_TAP_CMD_BYPASS 0xF
#define MASTER_TAP_CMD_IDCODE 0x2 #define MASTER_TAP_CMD_IDCODE 0x2
#define MASTER_TAP_CMD_TLM_SEL 0x5 #define MASTER_TAP_CMD_TLM_SEL 0x5
#define MASTER_TAP_CMD_FLASH_ERASE 0x8 #define MASTER_TAP_CMD_FLASH_ERASE 0x8
//---------------------------------------------------------------- /**
* ----------------------------------------------------------------
*/
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// EOnCE control register info * EOnCE control register info
//---------------------------------------------------------------- * ----------------------------------------------------------------
*/
#define DSP5680XX_ONCE_OCR_EX (1<<5) #define DSP5680XX_ONCE_OCR_EX (1<<5)
/* EX Bit Definition /* EX Bit Definition
0 Remain in the Debug Processing State 0 Remain in the Debug Processing State
1 Leave the Debug Processing State */ 1 Leave the Debug Processing State */
#define DSP5680XX_ONCE_OCR_GO (1<<6) #define DSP5680XX_ONCE_OCR_GO (1<<6)
/* GO Bit Definition /* GO Bit Definition
0 Inactive—No Action Taken 0 Inactive—No Action Taken
1 Execute Controller Instruction */ 1 Execute Controller Instruction */
#define DSP5680XX_ONCE_OCR_RW (1<<7) #define DSP5680XX_ONCE_OCR_RW (1<<7)
/* RW Bit Definition /** RW Bit Definition
0 Write To the Register Specified by the RS[4:0] Bits * 0 Write To the Register Specified by the RS[4:0] Bits
1 ReadFrom the Register Specified by the RS[4:0] Bits */ * 1 ReadFrom the Register Specified by the RS[4:0] Bits
//---------------------------------------------------------------- * ----------------------------------------------------------------
*/
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// EOnCE Status Register * EOnCE Status Register
//---------------------------------------------------------------- * ----------------------------------------------------------------
#define DSP5680XX_ONCE_OSCR_OS1 (1<<5) */
#define DSP5680XX_ONCE_OSCR_OS0 (1<<4) #define DSP5680XX_ONCE_OSCR_OS1 (1<<5)
//---------------------------------------------------------------- #define DSP5680XX_ONCE_OSCR_OS0 (1<<4)
/**
* ----------------------------------------------------------------
*/
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// EOnCE Core Status - Describes the operating status of the core controller * EOnCE Core Status - Describes the operating status of the core controller
//---------------------------------------------------------------- * ----------------------------------------------------------------
*/
#define DSP5680XX_ONCE_OSCR_NORMAL_M (0) #define DSP5680XX_ONCE_OSCR_NORMAL_M (0)
//00 - Normal - Controller Core Executing Instructions or in Reset /* 00 - Normal - Controller Core Executing Instructions or in Reset */
#define DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0) #define DSP5680XX_ONCE_OSCR_STOPWAIT_M (DSP5680XX_ONCE_OSCR_OS0)
//01 - Stop/Wait - Controller Core in Stop or Wait Mode /* 01 - Stop/Wait - Controller Core in Stop or Wait Mode */
#define DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1) #define DSP5680XX_ONCE_OSCR_BUSY_M (DSP5680XX_ONCE_OSCR_OS1)
//10 - Busy - Controller is Performing External or Peripheral Access (Wait States) /* 10 - Busy - Controller is Performing External or Peripheral Access (Wait States) */
#define DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1) #define DSP5680XX_ONCE_OSCR_DEBUG_M (DSP5680XX_ONCE_OSCR_OS0|DSP5680XX_ONCE_OSCR_OS1)
//11 - Debug - Controller Core Halted and in Debug Mode /* 11 - Debug - Controller Core Halted and in Debug Mode */
#define EONCE_STAT_MASK 0x30 #define EONCE_STAT_MASK 0x30
//---------------------------------------------------------------- /**
* ----------------------------------------------------------------
*/
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// Register Select Encoding (eonce_rev.1.0_0208081.pdf@14) * Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
//---------------------------------------------------------------- * ----------------------------------------------------------------
#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */ */
#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */ #define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */ #define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */ #define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */ #define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */
#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */ #define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */
#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */ #define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */
#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */ #define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */
#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */ #define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */
#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */ #define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */ #define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */ #define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */ #define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */ #define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */ #define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */ #define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */ #define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */ #define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */ #define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
//---------------------------------------------------------------- #define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
/**
* ----------------------------------------------------------------
*/
#define FLUSH_COUNT_READ_WRITE 8192 // This value works, higher values (and lower...) may work as well. #define FLUSH_COUNT_READ_WRITE 8192 // This value works, higher values (and lower...) may work as well.
#define FLUSH_COUNT_FLASH 8192 #define FLUSH_COUNT_FLASH 8192
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// HFM (flash module) Commands (ref:MC56F801xRM.pdf@159) * HFM (flash module) Commands (ref:MC56F801xRM.pdf@159)
//---------------------------------------------------------------- * ----------------------------------------------------------------
#define HFM_ERASE_VERIFY 0x05 */
#define HFM_ERASE_VERIFY 0x05
#define HFM_CALCULATE_DATA_SIGNATURE 0x06 #define HFM_CALCULATE_DATA_SIGNATURE 0x06
#define HFM_WORD_PROGRAM 0x20 #define HFM_WORD_PROGRAM 0x20
#define HFM_PAGE_ERASE 0x40 #define HFM_PAGE_ERASE 0x40
#define HFM_MASS_ERASE 0x41 #define HFM_MASS_ERASE 0x41
#define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66 #define HFM_CALCULATE_IFR_BLOCK_SIGNATURE 0x66
//---------------------------------------------------------------- /**
* ----------------------------------------------------------------
*/
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// Flashing (ref:MC56F801xRM.pdf@159) * Flashing (ref:MC56F801xRM.pdf@159)
//---------------------------------------------------------------- * ----------------------------------------------------------------
#define HFM_BASE_ADDR 0x0F400 // In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR to get data into x: mem.) */
// The following are register addresses, not memory addresses (though all registers are memory mapped) #define HFM_BASE_ADDR 0x0F400 /** In x: mem. (write to S_FILE_DATA_OFFSET+HFM_BASE_ADDR
#define HFM_CLK_DIV 0x00 // r/w * to get data into x: mem.)
#define HFM_CNFG 0x01 // r/w */
#define HFM_SECHI 0x03 // r /**
#define HFM_SECLO 0x04 // r * The following are register addresses, not memory
#define HFM_PROT 0x10 // r/w * addresses (though all registers are memory mapped)
#define HFM_PROTB 0x11 // r/w */
#define HFM_USTAT 0x13 // r/w #define HFM_CLK_DIV 0x00 /* r/w */
#define HFM_CMD 0x14 // r/w #define HFM_CNFG 0x01 /* r/w */
#define HFM_DATA 0x18 // r #define HFM_SECHI 0x03 /* r */
#define HFM_OPT1 0x1B // r #define HFM_SECLO 0x04 /* r */
#define HFM_TSTSIG 0x1D // r #define HFM_PROT 0x10 /* r/w */
#define HFM_PROTB 0x11 /* r/w */
#define HFM_USTAT 0x13 /* r/w */
#define HFM_CMD 0x14 /* r/w */
#define HFM_DATA 0x18 /* r */
#define HFM_OPT1 0x1B /* r */
#define HFM_TSTSIG 0x1D /* r */
#define HFM_EXEC_COMPLETE 0x40 #define HFM_EXEC_COMPLETE 0x40
// User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5) /* User status register (USTAT) masks (MC56F80XXRM.pdf@6.7.5) */
#define HFM_USTAT_MASK_BLANK 0x4 #define HFM_USTAT_MASK_BLANK 0x4
#define HFM_USTAT_MASK_PVIOL_ACCER 0x30 #define HFM_USTAT_MASK_PVIOL_ACCER 0x30
@ -182,11 +206,11 @@
#define HFM_CLK_DEFAULT 0x27 #define HFM_CLK_DEFAULT 0x27
/* 0x27 according to freescale cfg, but 0x40 according to freescale spreadsheet... */ /* 0x27 according to freescale cfg, but 0x40 according to freescale spreadsheet... */
#define HFM_FLASH_BASE_ADDR 0x0 #define HFM_FLASH_BASE_ADDR 0x0
#define HFM_SIZE_BYTES 0x4000 // bytes #define HFM_SIZE_BYTES 0x4000 /* bytes */
#define HFM_SIZE_WORDS 0x2000 // words #define HFM_SIZE_WORDS 0x2000 /* words */
#define HFM_SECTOR_SIZE 0x200 // Size in bytes #define HFM_SECTOR_SIZE 0x200 /* Size in bytes */
#define HFM_SECTOR_COUNT 0x20 #define HFM_SECTOR_COUNT 0x20
// A 16K block in pages of 256 words. /* A 16K block in pages of 256 words. */
/** /**
* Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset. * Writing HFM_LOCK_FLASH to HFM_LOCK_ADDR_L and HFM_LOCK_ADDR_H will enable security on flash after the next reset.
@ -194,26 +218,34 @@
#define HFM_LOCK_FLASH 0xE70A #define HFM_LOCK_FLASH 0xE70A
#define HFM_LOCK_ADDR_L 0x1FF7 #define HFM_LOCK_ADDR_L 0x1FF7
#define HFM_LOCK_ADDR_H 0x1FF8 #define HFM_LOCK_ADDR_H 0x1FF8
//---------------------------------------------------------------- /**
* ----------------------------------------------------------------
*/
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// Register Memory Map (eonce_rev.1.0_0208081.pdf@16) * Register Memory Map (eonce_rev.1.0_0208081.pdf@16)
//---------------------------------------------------------------- * ----------------------------------------------------------------
*/
#define MC568013_EONCE_OBASE_ADDR 0xFF #define MC568013_EONCE_OBASE_ADDR 0xFF
// The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) /* The following are relative to EONCE_OBASE_ADDR (EONCE_OBASE_ADDR<<16 + ...) */
#define MC568013_EONCE_TX_RX_ADDR 0xFFFE // #define MC568013_EONCE_TX_RX_ADDR 0xFFFE
#define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF // Relative to EONCE_OBASE_ADDR #define MC568013_EONCE_TX1_RX1_HIGH_ADDR 0xFFFF /* Relative to EONCE_OBASE_ADDR */
#define MC568013_EONCE_OCR 0xFFA0 // Relative to EONCE_OBASE_ADDR #define MC568013_EONCE_OCR 0xFFA0 /* Relative to EONCE_OBASE_ADDR */
//---------------------------------------------------------------- /**
* ----------------------------------------------------------------
*/
//---------------------------------------------------------------- /** ----------------------------------------------------------------
// SIM addresses & commands (MC56F80xx.h from freescale) * SIM addresses & commands (MC56F80xx.h from freescale)
//---------------------------------------------------------------- * ----------------------------------------------------------------
*/
#define MC568013_SIM_BASE_ADDR 0xF140 #define MC568013_SIM_BASE_ADDR 0xF140
#define MC56803x_2x_SIM_BASE_ADDR 0xF100 #define MC56803x_2x_SIM_BASE_ADDR 0xF100
#define SIM_CMD_RESET 0x10 #define SIM_CMD_RESET 0x10
//---------------------------------------------------------------- /**
* ----------------------------------------------------------------
*/
/** /**
* ---------------------------------------------------------------- * ----------------------------------------------------------------
@ -253,17 +285,18 @@
* ---------------------------------------------------------------- * ----------------------------------------------------------------
*/ */
struct dsp5680xx_common{ struct dsp5680xx_common {
//TODO uint32_t stored_pc;
uint32_t stored_pc; int flush;
int flush; bool debug_mode_enabled;
bool debug_mode_enabled;
}; };
extern struct dsp5680xx_common dsp5680xx_context; extern struct dsp5680xx_common dsp5680xx_context;
static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target){ static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target
return target->arch_info; *target)
{
return target->arch_info;
} }
/** /**
@ -279,7 +312,8 @@ static inline struct dsp5680xx_common *target_to_dsp5680xx(struct target *target
* *
* @return * @return
*/ */
int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, uint32_t count, int is_flash_lock); int dsp5680xx_f_wr(struct target *target, uint8_t * buffer, uint32_t address,
uint32_t count, int is_flash_lock);
/** /**
* The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis. * The FM has the funcionality of checking if the flash array is erased. This function executes it. It does not support individual sector analysis.
@ -290,7 +324,8 @@ int dsp5680xx_f_wr(struct target * target, uint8_t *buffer, uint32_t address, ui
* *
* @return * @return
*/ */
int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased, uint32_t sector); int dsp5680xx_f_erase_check(struct target *target, uint8_t * erased,
uint32_t sector);
/** /**
* Erases either a sector or the complete flash array. If either the range first-last covers the complete array or if @first == 0 and @last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased. * Erases either a sector or the complete flash array. If either the range first-last covers the complete array or if @first == 0 and @last == 0 then a mass erase command is executed on the FM. If not, then individual sectors are erased.
@ -301,7 +336,7 @@ int dsp5680xx_f_erase_check(struct target * target,uint8_t * erased, uint32_t se
* *
* @return * @return
*/ */
int dsp5680xx_f_erase(struct target * target, int first, int last); int dsp5680xx_f_erase(struct target *target, int first, int last);
/** /**
* Reads the memory mapped protection register. A 1 implies the sector is protected, a 0 implies the sector is not protected. * Reads the memory mapped protection register. A 1 implies the sector is protected, a 0 implies the sector is not protected.
@ -311,7 +346,7 @@ int dsp5680xx_f_erase(struct target * target, int first, int last);
* *
* @return * @return
*/ */
int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected); int dsp5680xx_f_protect_check(struct target *target, uint16_t * protected);
/** /**
* Writes the flash security words with a specific value. The chip's security will be enabled after the first reset following the execution of this function. * Writes the flash security words with a specific value. The chip's security will be enabled after the first reset following the execution of this function.
@ -320,7 +355,7 @@ int dsp5680xx_f_protect_check(struct target * target, uint16_t * protected);
* *
* @return * @return
*/ */
int dsp5680xx_f_lock(struct target * target); int dsp5680xx_f_lock(struct target *target);
/** /**
* Executes a mass erase command. The must be done from the Master tap. * Executes a mass erase command. The must be done from the Master tap.
@ -331,6 +366,6 @@ int dsp5680xx_f_lock(struct target * target);
* *
* @return * @return
*/ */
int dsp5680xx_f_unlock(struct target * target); int dsp5680xx_f_unlock(struct target *target);
#endif // dsp5680xx.h #endif /* dsp5680xx.h */