Submitted by David Brownell <david-b@pacbell.net>:
Improve support for the DM355 EVM board, and eventually other boards based on DaVinci chips: - Provide generic "davinci.cfg" to hold utilities that can be reused by different chips in this family. Start with PINMUX, PSC, and PLL setup. - DM355 chip support updates: provide a dictionary with chip-specific symbols, load those utilities. - Create a new dm355evm board file, with a reset-init event handler which uses those utilities to set up PLLs and clocks, configure the pins, and improve the JTAG speed limit. Also a minor tweak: provide a virtual address for the work area, matching what the very latest kernels do. It's probably unwise to use OpenOCD while the MMU is active though. The DRAM isn't yet accessible, but NAND access is mostly ready. git-svn-id: svn://svn.berlios.de/openocd/trunk@1881 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
zwelch
parent
ebd3f88798
commit
3d0b474da9
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@ -0,0 +1,111 @@
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#
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# DM355 EVM board
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# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
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# http://c6000.spectrumdigital.com/evmdm355/
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source [find target/ti_dm355.cfg]
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reset_config trst_and_srst separate
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# NOTE: disable or replace this call to dm355evm_init if you're
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# debugging new UBL code from SRAM.
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$_TARGETNAME configure -event reset-init { dm355evm_init }
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#
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# This post-reset init is called when the MMU isn't active, all IRQs
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# are disabled, etc. It should do most of what a UBL does, except for
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# loading code (like U-Boot) into DRAM and running it.
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#
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proc dm355evm_init {} {
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global dm355
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puts "Initialize DM355 EVM board"
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# CLKIN = 24 MHz ... can't talk quickly to ARM yet
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jtag_khz 1500
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########################
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# PLL1 = 432 MHz (/8, x144)
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# ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
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# ...SYSCLK2 = 108 MHz (/4) ... Peripherals
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# ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
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# ...SYSCLK4 = 108 MHz (/4) ... VPSS
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# pll1.{prediv,div1,div2} are fixed
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# pll1.postdiv set in MISC (for *this* speed grade)
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set addr [dict get $dm355 pllc1]
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set pll_divs [dict create]
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dict set pll_divs div3 16
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dict set pll_divs div4 8
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pll_setup $addr 144 $pll_divs
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# ARM is now running at 216 MHz, so JTAG can go faster
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jtag_khz 20000
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########################
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# PLL2 = 342 MHz (/8, x114)
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# ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
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# pll2.{postdiv,div1} are fixed
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set addr [dict get $dm355 pllc2]
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set pll_divs [dict create]
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dict set pll_divs prediv 8
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pll_setup $addr 114 $pll_divs
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########################
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# PINMUX
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# All Video Inputs
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davinci_pinmux $dm355 0 0x00007f55
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# All Video Outputs
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davinci_pinmux $dm355 1 0x00145555
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# EMIFA (NOTE: more could be set up for use as GPIOs)
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davinci_pinmux $dm355 2 0x00000c08
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# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
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davinci_pinmux $dm355 3 0x1bff55ff
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# MMC/SD0 instead of MS; SPI0
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davinci_pinmux $dm355 4 0x00000000
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########################
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# PSC setup (minimal)
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# DDR EMIF/13, AEMIF/14, UART0/19
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psc_enable 13
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psc_enable 14
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psc_enable 19
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psc_go
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########################
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# DDR2 EMIF
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# FIXME setup
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########################
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# ASYNC EMIF
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set addr [dict get $dm355 a_emif]
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# slow/pessimistic timings
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set nand_timings 0x40400204
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# fast (25% faster page reads)
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#set nand_timings 0x0400008c
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# AWCCR
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mww [expr $addr + 0x04] 0xff
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# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
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mww [expr $addr + 0x10] $nand_timings
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# CS1 == dm9000 Ethernet
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mww [expr $addr + 0x14] 0x00a00505
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# NANDFCR -- only CS0 has NAND
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mww [expr $addr + 0x60] 0x01
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########################
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# UART0
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# FIXME setup
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}
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# FIXME
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# - declare the NAND flash; use the 4-bit ECC
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# - support writing UBL with its header (new layout only with new ROMs)
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# - support writing ABL/U-Boot with its header (both layouts)
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@ -0,0 +1,170 @@
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#
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# Utility code for DaVinci-family chips
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#
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# davinci_pinmux: assigns PINMUX$reg <== $value
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proc davinci_pinmux {soc reg value} {
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mww [expr [dict get $soc sysbase] + 4 * $reg] $value
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}
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# mrw: "memory read word", returns value of $reg
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proc mrw {reg} {
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set value ""
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ocd_mem2array value 32 $reg 1
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return $value(0)
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}
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# mmw: "memory modify word", updates value of $reg
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# $reg <== ((value & ~$clearbits) | $setbits)
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proc mmw {reg setbits clearbits} {
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set old [mrw $reg]
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set new [expr ($old & ~$clearbits) | $setbits]
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mww $reg $new
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}
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#
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# pll_setup: initialize PLL
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# - pll_addr ... physical addr of controller
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# - mult ... pll multiplier
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# - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
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#
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# For PLLs that don't have a given register (e.g. plldiv8), or where a
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# given divider is non-programmable, caller provides *NO* config mapping.
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#
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# REVISIT there are minor differences between the PLL controllers.
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# Handle those; maybe check the ID register. This version behaves
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# for at least the dm355. On dm6446 and dm357 the PLLRST polarity
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# is different. On dm365 there are more changes.
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#
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proc pll_setup {pll_addr mult config} {
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set pll_ctrl_addr [expr $pll_addr + 0x100]
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set pll_ctrl [mrw $pll_ctrl_addr]
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# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
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# NOTE: this assumes we should clear that bit
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set pll_ctrl [expr $pll_ctrl & ~0x0100]
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mww $pll_ctrl_addr $pll_ctrl
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# 2 - clear PLLENSRC (bit 5)
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set pll_ctrl [expr $pll_ctrl & ~0x0020]
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mww $pll_ctrl_addr $pll_ctrl
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# 3 - clear PLLEN (bit 0) ... enter bypass mode
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set pll_ctrl [expr $pll_ctrl & ~0x0001]
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mww $pll_ctrl_addr $pll_ctrl
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# 4 - wait at least 4 refclk cycles
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sleep 1
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# 5 - set PLLRST (bit 3)
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set pll_ctrl [expr $pll_ctrl | 0x0008]
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mww $pll_ctrl_addr $pll_ctrl
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# 6 - set PLLDIS (bit 4)
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set pll_ctrl [expr $pll_ctrl | 0x0010]
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mww $pll_ctrl_addr $pll_ctrl
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# 7 - clear PLLPWRDN (bit 1)
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set pll_ctrl [expr $pll_ctrl & ~0x0002]
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mww $pll_ctrl_addr $pll_ctrl
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# 8 - clear PLLDIS (bit 4)
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set pll_ctrl [expr $pll_ctrl & ~0x0010]
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mww $pll_ctrl_addr $pll_ctrl
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# 9 - optional: write prediv, postdiv, and pllm
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# NOTE: for dm355 PLL1, postdiv is controlled via MISC register
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mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
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if { [dict exists $config prediv] } {
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set div [dict get $config prediv]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0114] $div
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}
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if { [dict exists $config postdiv] } {
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set div [dict get $config postdiv]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0128] $div
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}
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# 10 - optional: set plldiv1, plldiv2, ...
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# NOTE: this assumes some registers have their just-reset values:
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# - PLLSTAT.GOSTAT is clear when we enter
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# - ALNCTL has everything set
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set go 0
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if { [dict exists $config div1] } {
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set div [dict get $config div1]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0118] $div
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set go 1
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}
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if { [dict exists $config div2] } {
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1et div [dict get $config div2]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x011c] $div
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set go 1
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}
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if { [dict exists $config div3] } {
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set div [dict get $config div3]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x011c] $div
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set go 1
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}
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if { [dict exists $config div4] } {
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set div [dict get $config div4]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0160] $div
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set go 1
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}
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if { [dict exists $config div5] } {
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set div [dict get $config div5]
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set div [expr 0x8000 | ($div - 1)]
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mww [expr $pll_addr + 0x0164] $div
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set go 1
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}
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if {$go != 0} {
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# write pllcmd.GO; poll pllstat.GO
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mww [expr $pll_addr + 0x0138] 0x01
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set pllstat [expr $pll_addr + 0x013c]
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while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
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}
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# 11 - wait at least 5 usec for reset to finish
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# (assume covered by overheads including JTAG messaging)
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# 12 - clear PLLRST (bit 3)
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set pll_ctrl [expr $pll_ctrl & ~0x0008]
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mww $pll_ctrl_addr $pll_ctrl
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# 13 - wait at least 8000 refclk cycles for PLL to lock
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# if we assume 24 MHz (slowest osc), that's 1/3 msec
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sleep 3
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# 14 - set PLLEN (bit 0) ... leave bypass mode
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set pll_ctrl [expr $pll_ctrl | 0x0001]
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mww $pll_ctrl_addr $pll_ctrl
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}
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# NOTE: dm6446 requires EMURSTIE set in MDCTL before certain
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# modules can be enabled.
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# prepare a non-DSP module to be enabled; finish with psc_go
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proc psc_enable {module} {
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set psc_addr 0x01c41000
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# write MDCTL
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mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
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}
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# execute non-DSP PSC transition(s) set up by psc_enable
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proc psc_go {} {
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set psc_addr 0x01c41000
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set ptstat_addr [expr $psc_addr + 0x0128]
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# just in case PTSTAT.go isn't clear
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while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
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# write PTCMD.go ... ignoring any DSP power domain
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mww [expr $psc_addr + 0x0120] 1
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# wait for PTSTAT.go to clear (again ignoring DSP power domain)
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while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
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}
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@ -44,12 +44,44 @@ if { [info exists JRC_TAPID ] } {
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}
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
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################
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# various symbol definitions, to avoid hard-wiring addresses
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# and enable some sharing of DaVinci-family utility code
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global dm355
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set dm355 [ dict create ]
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# Physical addresses for controllers and memory
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# (Some of these are valid for many DaVinci family chips)
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dict set dm355 sram0 0x00010000
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dict set dm355 sram1 0x00014000
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dict set dm355 sysbase 0x01c40000
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dict set dm355 pllc1 0x01c40800
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dict set dm355 pllc2 0x01c40c00
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dict set dm355 psc 0x01c41000
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dict set dm355 gpio 0x01c67000
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dict set dm355 a_emif 0x01e10000
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dict set dm355 a_emif_cs0 0x02000000
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dict set dm355 a_emif_cs1 0x04000000
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dict set dm355 ddr_emif 0x20000000
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dict set dm355 ddr 0x80000000
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source [find target/davinci.cfg]
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################
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# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
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# and the ETB memory (4K) are other options, while trace is unused.
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set _TARGETNAME $_CHIPNAME.arm
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00014000 -work-area-size 0x4000 -work-area-backup 0
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# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
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# and that the work area is used only with a kernel mmu context ...
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$_TARGETNAME configure \
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-work-area-virt [expr 0xfffe0000 + 0x4000] \
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-work-area-phys [dict get $dm355 sram1] \
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-work-area-size 0x4000 \
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-work-area-backup 0
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arm7_9 dbgrq enable
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arm7_9 fast_memory_access enable
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