rtos: Fix XPSR_OFFSET for cortex_m4f stacking
Structures rtos_standard_Cortex_M4F_stacking and rtos_standard_Cortex_M4F_FPU_stacking in rtos_standard_stackings.c where using rtos_standard_Cortex_M3_stack_align for the stack-align function. This function calls rtos_Cortex_M_stack_align with XPSR_OFFSET = 0x3c. This offset is correct for cortex-M3 but not for cortex-M4F and cortex-M4F with fpu. This patch adds stack_align functions for M4F an M4F_FPU Change-Id: If6a90b1898fccbb85619a10f3aef5277dd88ce47 Signed-off-by: Armin van der Togt <armin@otheruse.nl> Reviewed-on: http://openocd.zylin.com/4037 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>riscv-compliance-dev^2
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4c8e7a0486
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3c7fd99832
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@ -229,6 +229,25 @@ static int64_t rtos_standard_Cortex_M3_stack_align(struct target *target,
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stack_ptr, XPSR_OFFSET);
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stack_ptr, XPSR_OFFSET);
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}
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}
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static int64_t rtos_standard_Cortex_M4F_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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int64_t stack_ptr)
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{
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const int XPSR_OFFSET = 0x40;
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return rtos_Cortex_M_stack_align(target, stack_data, stacking,
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stack_ptr, XPSR_OFFSET);
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}
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static int64_t rtos_standard_Cortex_M4F_FPU_stack_align(struct target *target,
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const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
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int64_t stack_ptr)
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{
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const int XPSR_OFFSET = 0x80;
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return rtos_Cortex_M_stack_align(target, stack_data, stacking,
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stack_ptr, XPSR_OFFSET);
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}
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const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
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const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
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0x40, /* stack_registers_size */
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0x40, /* stack_registers_size */
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-1, /* stack_growth_direction */
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-1, /* stack_growth_direction */
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@ -241,7 +260,7 @@ const struct rtos_register_stacking rtos_standard_Cortex_M4F_stacking = {
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0x44, /* stack_registers_size 4 more for LR*/
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0x44, /* stack_registers_size 4 more for LR*/
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-1, /* stack_growth_direction */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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rtos_standard_Cortex_M3_stack_align, /* stack_alignment */
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rtos_standard_Cortex_M4F_stack_align, /* stack_alignment */
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rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */
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rtos_standard_Cortex_M4F_stack_offsets /* register_offsets */
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};
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};
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@ -249,7 +268,7 @@ const struct rtos_register_stacking rtos_standard_Cortex_M4F_FPU_stacking = {
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0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
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0xcc, /* stack_registers_size 4 more for LR + 48 more for FPU S0-S15 register*/
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-1, /* stack_growth_direction */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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rtos_standard_Cortex_M3_stack_align, /* stack_alignment */
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rtos_standard_Cortex_M4F_FPU_stack_align, /* stack_alignment */
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rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */
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rtos_standard_Cortex_M4F_FPU_stack_offsets /* register_offsets */
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};
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};
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