Checkpoint: finish debug of tests, working on hitting sbbusyerror case
Ryan Macdonald
parent
c5a8e1cf4c
commit
3bdb8b29a8
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@ -57,7 +57,7 @@ static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a,
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static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a);
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static int riscv013_dmi_write_u64_bits(struct target *target);
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static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf);
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static int riscv013_test_sba_config_reg(struct target *target, uint32_t address);
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static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address);
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uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs);
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void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs);
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static int register_read_direct(struct target *target, uint64_t *value, uint32_t number);
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@ -1491,7 +1491,7 @@ static int init_target(struct command_context *cmd_ctx,
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generic_info->fill_dmi_read_u64 = &riscv013_fill_dmi_read_u64;
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generic_info->fill_dmi_nop_u64 = &riscv013_fill_dmi_nop_u64;
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generic_info->dmi_write_u64_bits = &riscv013_dmi_write_u64_bits;
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generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg;
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generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg;
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generic_info->authdata_read = &riscv013_authdata_read;
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generic_info->authdata_write = &riscv013_authdata_write;
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generic_info->dmi_read = &dmi_read;
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@ -2815,160 +2815,242 @@ void riscv013_fill_dmi_nop_u64(struct target *target, char *buf)
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buf_set_u64((unsigned char *)buf, DTM_DMI_ADDRESS_OFFSET, info->abits, 0);
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}
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static int riscv013_test_sba_config_reg(struct target *target, uint32_t address)
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static int get_max_sbaccess(struct target *target)
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{
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LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13");
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uint32_t sbcs;
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dmi_read(target,&sbcs,DMI_SBCS);
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if(!riscv_rtos_enabled(target)) {
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LOG_ERROR("Please run with -rtos riscv to run SBA test.");
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}
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uint32_t sbaccess128 = get_field(sbcs, DMI_SBCS_SBACCESS128);
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uint32_t sbaccess64 = get_field(sbcs, DMI_SBCS_SBACCESS64);
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uint32_t sbaccess32 = get_field(sbcs, DMI_SBCS_SBACCESS32);
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uint32_t sbaccess16 = get_field(sbcs, DMI_SBCS_SBACCESS16);
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uint32_t sbaccess8 = get_field(sbcs, DMI_SBCS_SBACCESS8);
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uint32_t rd_val;
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uint32_t sbcs_orig;
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dmi_read(target, &sbcs_orig, DMI_SBCS);
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if(sbaccess128){
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return 4;
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}else if(sbaccess64){
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return 3;
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}else if(sbaccess32){
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return 2;
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}else if(sbaccess16){
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return 1;
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}else if(sbaccess8){
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return 0;
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} else {
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return ERROR_FAIL;
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}
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}
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uint32_t sbcs = sbcs_orig;
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static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address)
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{
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LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13");
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// Test 1: Simple write/read test, no address autoincrement
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBAUTOINCREMENT,0);
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dmi_write(target,DMI_SBCS,sbcs);
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uint32_t rd_val;
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uint32_t sbcs_orig;
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dmi_read(target, &sbcs_orig, DMI_SBCS)
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for(int sbaccess = 0; sbaccess < 0x5; sbaccess++) {
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,sbaccess);
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dmi_write(target,DMI_SBCS,sbcs);
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uint32_t sbcs = sbcs_orig;
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bool test_passed;
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for(int i = 0; i < 100; i++){
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uint32_t addr = 0x80000000 + (i << sbaccess);
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write_memory_sba_simple(target,addr,i,sbcs_orig);
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}
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int max_sbaccess = get_max_sbaccess(target);
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for(uint32_t i = 0; i < 100; i++){
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uint32_t addr = 0x80000000 + (i << sbaccess);
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uint32_t val = read_memory_sba_simple(target,addr,sbcs_orig);
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if(i != val) {
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LOG_ERROR("System Bus Access Test: Error reading non-autoincremented address %x, expected val = %d, read val = %d",addr,i,val);
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}
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}
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}
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LOG_INFO("System Bus Access Test: Read/write test, no addr autoincrement PASSED");
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if(max_sbaccess == ERROR_FAIL) {
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LOG_ERROR("System Bus Access not supported in this config.");
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return ERROR_FAIL;
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}
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// Test 2: Simple write/read test, with address autoincrement
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBAUTOINCREMENT,1);
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dmi_write(target,DMI_SBCS,sbcs);
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if(get_field(sbcs, DMI_SBCS_SBVERSION) != 1) {
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LOG_ERROR("System Bus Access unsupported SBVERSION");
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return ERROR_FAIL;
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}
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for(int sbaccess = 0; sbaccess < 0x5; sbaccess++){
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,sbaccess);
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dmi_write(target,DMI_SBCS,sbcs);
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// Test 1: Simple write/read test, no address autoincrement
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test_passed = true;
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 0);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_write(target,DMI_SBADDRESS0,0x80000000);
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for(int i = 0; i < 100; i++){
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read_sbcs_nonbusy(target,&sbcs);
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dmi_write(target,DMI_SBDATA0,i);
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}
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for(int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++){
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sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess);
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dmi_write(target, DMI_SBCS, sbcs);
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBREADONDATA,1);
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for(int i = 0; i < 100; i++){
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uint32_t addr = 0x80000000 + (i << sbaccess);
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write_memory_sba_simple(target, addr, i, sbcs);
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}
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dmi_write(target,DMI_SBADDRESS0,0x80000000);
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for(uint32_t i = 0; i < 100; i++){
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read_sbcs_nonbusy(target,&sbcs);
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uint32_t val;
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dmi_read(target,&val,DMI_SBDATA0);
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if(i != val) {
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LOG_ERROR("System Bus Access Test: Error reading autoincremented address, expected val = %d, read val = %d",i,val);
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}
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}
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}
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LOG_INFO("System Bus Access Test: Read/write test, with addr autoincrement PASSED");
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for(uint32_t i = 0; i < 100; i++){
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uint32_t addr = 0x80000000 + (i << sbaccess);
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uint32_t val = read_memory_sba_simple(target, addr, sbcs);
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if(i != val) {
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LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %d, read val = %d", addr, i, val);
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test_passed = false;
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}
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}
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}
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if(test_passed) LOG_INFO("System Bus Access Test 1: Read/write test, no addr autoincrement PASSED");
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// Test 3: Read from illegal address
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read_memory_sba_simple(target,address,sbcs_orig);
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// Test 2: Simple write/read test, with address autoincrement
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test_passed = true;
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBAUTOINCREMENT, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target,&rd_val,DMI_SBCS);
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if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x2) {
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LOG_INFO("System Bus Access Test: Illegal address read test PASSED");
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,1);
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dmi_write(target,DMI_SBCS,sbcs);
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} else {
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LOG_ERROR("System Bus Access Test: Illegal address read test FAILED");
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}
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for(int sbaccess = 0; sbaccess <= max_sbaccess; sbaccess++){
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sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess);
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dmi_write(target, DMI_SBCS, sbcs);
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// Test 4: Write to illegal address
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write_memory_sba_simple(target,address,0xdeadbeef,sbcs_orig);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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for(int i = 0; i < 100; i++){
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read_sbcs_nonbusy(target, &sbcs);
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dmi_write(target, DMI_SBDATA0, i);
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}
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dmi_read(target,&rd_val,DMI_SBCS);
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if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x2) {
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LOG_INFO("System Bus Access Test: Illegal address write test PASSED");
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,1);
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dmi_write(target,DMI_SBCS,sbcs);
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} else {
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LOG_ERROR("System Bus Access Test: Illegal address write test FAILED");
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}
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read_sbcs_nonbusy(target, &sbcs);
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// Test 5: Write to unsupported sbaccess size
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uint32_t sbaccess128 = get_field(sbcs_orig,DMI_SBCS_SBACCESS128);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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if(sbaccess128) {
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LOG_INFO("System Bus Access Test: SBCS Alignment error test PASSED, all alignments supported");
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} else {
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBACCESS,0x4);
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dmi_write(target, DMI_SBCS, sbcs);
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uint32_t val;
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sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target, &val, DMI_SBDATA0); // Dummy read to trigger first system bus read
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for(uint32_t i = 0; i < 100; i++){
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read_sbcs_nonbusy(target, &sbcs);
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dmi_read(target, &val, DMI_SBDATA0);
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read_sbcs_nonbusy(target, &sbcs);
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if(i != val) {
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LOG_ERROR("System Bus Access Test 2: Error reading autoincremented address, expected val = %d, read val = %d",i,val);
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test_passed = false;
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}
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}
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}
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if(test_passed) LOG_INFO("System Bus Access Test 2: Read/write test, addr autoincrement PASSED");
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write_memory_sba_simple(target, 0x80000000, 0xdeadbeef, sbcs_orig);
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// Test 3: Read from illegal address
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read_memory_sba_simple(target, illegal_address, sbcs_orig);
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dmi_read(target,&rd_val,DMI_SBCS);
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dmi_read(target, &rd_val, DMI_SBCS);
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if(get_field(rd_val, DMI_SBCS_SBERROR) == 2) {
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LOG_INFO("System Bus Access Test 3: Illegal address read test PASSED");
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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} else {
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LOG_ERROR("System Bus Access Test 3: Illegal address read test FAILED");
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}
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if(get_field(rd_val,DMI_SBCS_SBERROR) == 0x3) {
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LOG_INFO("System Bus Access Test: SBCS Alignment error test PASSED");
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBERROR,0x1);
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dmi_write(target,DMI_SBCS,sbcs);
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} else {
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LOG_ERROR("System Bus Access Test: SBCS Alignment error test FAILED");
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}
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}
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// Test 5: Set sbbusyerror
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dmi_write(target,DMI_SBADDRESS0,0x80000000);
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dmi_write(target,DMI_SBADDRESS0,0x80000000);
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// Test 4: Write to illegal address
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write_memory_sba_simple(target, illegal_address, 0xdeadbeef, sbcs_orig);
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dmi_read(target,&rd_val,DMI_SBCS);
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if(get_field(rd_val,DMI_SBCS_SBBUSYERROR)) {
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LOG_INFO("System Bus Access Test: SBCS sbbusy test PASSED");
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sbcs = set_field(sbcs_orig,DMI_SBCS_SBBUSYERROR,0x1);
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dmi_write(target,DMI_SBCS,sbcs);
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} else {
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LOG_ERROR("System Bus Access Test: SBCS sbbusy test FAILED");
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}
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dmi_read(target, &rd_val, DMI_SBCS);
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if(get_field(rd_val, DMI_SBCS_SBERROR) == 2) {
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LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED");
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS,sbcs);
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} else {
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LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED");
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}
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return 0;
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// Test 5: Write to unsupported sbaccess size
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uint32_t sbaccess128 = get_field(sbcs_orig, DMI_SBCS_SBACCESS128);
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if(sbaccess128) {
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LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED, all alignments supported");
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} else {
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4);
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dmi_write(target, DMI_SBCS, sbcs);
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write_memory_sba_simple(target, 0x80000000, 0xdeadbeef, sbcs_orig);
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dmi_read(target, &rd_val, DMI_SBCS);
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if(get_field(rd_val, DMI_SBCS_SBERROR) == 3) {
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LOG_INFO("System Bus Access Test 5: SBCS Alignment error test PASSED");
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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} else {
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LOG_ERROR("System Bus Access Test 5: SBCS Alignment error test FAILED");
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}
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}
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// Test 6: Set sbbusyerror
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBREADONADDR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBDATA0, 0xdeadbeef);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_write(target, DMI_SBADDRESS0, 0x80000000);
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dmi_read(target, &rd_val, DMI_SBCS);
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if(get_field(rd_val,DMI_SBCS_SBBUSYERROR)) {
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sbcs = set_field(sbcs_orig, DMI_SBCS_SBBUSYERROR, 1);
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dmi_write(target, DMI_SBCS, sbcs);
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dmi_read(target, &rd_val, DMI_SBCS);
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if(get_field(rd_val, DMI_SBCS_SBBUSYERROR) == 0) LOG_INFO("System Bus Access Test 6: SBCS sbbusyerror test PASSED");
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else LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to clear to 0");
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} else {
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LOG_ERROR("System Bus Access Test 6: SBCS sbbusyerror test FAILED, unable to set");
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}
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return ERROR_OK;
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}
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void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs)
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{
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uint32_t rd_sbcs;
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read_sbcs_nonbusy(target,&rd_sbcs);
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uint32_t rd_sbcs;
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uint32_t sbcs_no_readonaddr = set_field(sbcs,DMI_SBCS_SBREADONADDR,0);
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dmi_write(target,DMI_SBCS,sbcs_no_readonaddr);
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dmi_write(target,DMI_SBADDRESS0,addr);
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dmi_write(target,DMI_SBDATA0,data);
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read_sbcs_nonbusy(target, &rd_sbcs);
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uint32_t sbcs_no_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 0);
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dmi_write(target, DMI_SBCS, sbcs_no_readonaddr);
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dmi_write(target, DMI_SBADDRESS0, addr);
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dmi_write(target, DMI_SBDATA0, data);
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}
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uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs)
|
||||
{
|
||||
uint32_t rd_val;
|
||||
uint32_t rd_sbcs;
|
||||
read_sbcs_nonbusy(target,&rd_sbcs);
|
||||
uint32_t rd_val;
|
||||
uint32_t rd_sbcs;
|
||||
|
||||
uint32_t sbcs_readonaddr = set_field(sbcs,DMI_SBCS_SBREADONADDR,1);
|
||||
dmi_write(target,DMI_SBCS,sbcs_readonaddr);
|
||||
dmi_write(target,DMI_SBADDRESS0,addr);
|
||||
read_sbcs_nonbusy(target, &rd_sbcs);
|
||||
|
||||
read_sbcs_nonbusy(target,&rd_sbcs);
|
||||
uint32_t sbcs_readonaddr = set_field(sbcs, DMI_SBCS_SBREADONADDR, 1);
|
||||
dmi_write(target, DMI_SBCS,sbcs_readonaddr);
|
||||
dmi_write(target, DMI_SBADDRESS0,addr);
|
||||
|
||||
dmi_read(target,&rd_val,DMI_SBDATA0);
|
||||
read_sbcs_nonbusy(target, &rd_sbcs);
|
||||
|
||||
return rd_val;
|
||||
dmi_read(target, &rd_val, DMI_SBDATA0);
|
||||
|
||||
return rd_val;
|
||||
}
|
||||
|
||||
int riscv013_dmi_write_u64_bits(struct target *target)
|
||||
|
|
|
|||
|
|
@ -1438,11 +1438,11 @@ COMMAND_HANDLER(riscv_test_sba_config_reg)
|
|||
struct target *target = get_current_target(CMD_CTX);
|
||||
RISCV_INFO(r);
|
||||
|
||||
uint32_t address;
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
|
||||
uint32_t illegal_address;
|
||||
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], illegal_address);
|
||||
|
||||
if (r->test_sba_config_reg) {
|
||||
return r->test_sba_config_reg(target,address);
|
||||
return r->test_sba_config_reg(target, illegal_address);
|
||||
} else {
|
||||
LOG_ERROR("test_sba_config_reg is not implemented for this target.");
|
||||
return ERROR_FAIL;
|
||||
|
|
@ -1520,8 +1520,8 @@ static const struct command_registration riscv_exec_command_handlers[] = {
|
|||
.name = "test_sba_config_reg",
|
||||
.handler = riscv_test_sba_config_reg,
|
||||
.mode = COMMAND_ANY,
|
||||
.usage = "riscv test_sba_config_reg address",
|
||||
.help = "Perform a series of tests on the SBCS register. Pass in a non-readable/writable address"
|
||||
.usage = "riscv test_sba_config_reg illegal_address",
|
||||
.help = "Perform a series of tests on the SBCS register. Input arg is a non-readable/writable address."
|
||||
},
|
||||
COMMAND_REGISTRATION_DONE
|
||||
};
|
||||
|
|
|
|||
|
|
@ -117,7 +117,7 @@ typedef struct {
|
|||
int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address);
|
||||
int (*dmi_write)(struct target *target, uint32_t address, uint32_t value);
|
||||
|
||||
int (*test_sba_config_reg)(struct target *target, uint32_t address);
|
||||
int (*test_sba_config_reg)(struct target *target, target_addr_t illegal_address);
|
||||
|
||||
} riscv_info_t;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue