From 3a550e5b5fe011e526b150a5d234b48e8e2aaad6 Mon Sep 17 00:00:00 2001 From: Spencer Oliver Date: Thu, 19 Jan 2012 10:06:37 +0000 Subject: [PATCH] cleanup: rename armv4_5 to arm for readability MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Nothing more than a name change, just to make reading the code a bit simpler. Change-Id: I73a16b7302b48ce07d9688162955aae71d11eb45 Signed-off-by: Spencer Oliver Reviewed-on: http://openocd.zylin.com/390 Tested-by: jenkins Reviewed-by: Øyvind Harboe --- src/flash/nand/arm_io.c | 8 +- src/flash/nor/str9xpec.c | 6 +- src/target/arm.h | 2 +- src/target/arm720t.c | 21 ++- src/target/arm720t.h | 2 +- src/target/arm7_9_common.c | 257 +++++++++++++++++-------------------- src/target/arm7_9_common.h | 4 +- src/target/arm7tdmi.c | 12 +- src/target/arm920t.c | 50 ++++---- src/target/arm920t.h | 2 +- src/target/arm926ejs.c | 18 +-- src/target/arm926ejs.h | 2 +- src/target/arm946e.h | 2 +- src/target/arm966e.h | 2 +- src/target/arm9tdmi.c | 13 +- src/target/arm_simulator.c | 40 +++--- src/target/armv4_5.c | 175 +++++++++++++------------ src/target/armv7a.c | 30 ++--- src/target/armv7a.h | 4 +- src/target/cortex_a.c | 138 ++++++++++---------- src/target/cortex_a.h | 2 +- src/target/feroceon.c | 108 ++++++++-------- src/target/xscale.c | 158 ++++++++++++----------- src/target/xscale.h | 4 +- 24 files changed, 526 insertions(+), 534 deletions(-) diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c index 7a6ceb399..431ac9083 100644 --- a/src/flash/nand/arm_io.c +++ b/src/flash/nand/arm_io.c @@ -97,7 +97,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) { struct target *target = nand->target; struct arm_algorithm algo; - struct arm *armv4_5 = target->arch_info; + struct arm *arm = target->arch_info; struct reg_param reg_params[3]; uint32_t target_buf; uint32_t exit_var = 0; @@ -152,7 +152,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) buf_set_u32(reg_params[2].value, 0, 32, size); /* armv4 must exit using a hardware breakpoint */ - if (armv4_5->is_armv4) + if (arm->is_armv4) exit_var = nand->copy_area->address + sizeof(code) - 4; /* use alg to write data from work area to NAND chip */ @@ -181,7 +181,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) { struct target *target = nand->target; struct arm_algorithm algo; - struct arm *armv4_5 = target->arch_info; + struct arm *arm = target->arch_info; struct reg_param reg_params[3]; uint32_t target_buf; uint32_t exit_var = 0; @@ -228,7 +228,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size) buf_set_u32(reg_params[2].value, 0, 32, size); /* armv4 must exit using a hardware breakpoint */ - if (armv4_5->is_armv4) + if (arm->is_armv4) exit_var = nand->copy_area->address + sizeof(code) - 4; /* use alg to write data from NAND chip to work area */ diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c index fc2ed3590..b598c2629 100644 --- a/src/flash/nor/str9xpec.c +++ b/src/flash/nor/str9xpec.c @@ -286,7 +286,7 @@ static int str9xpec_build_block_list(struct flash_bank *bank) FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command) { struct str9xpec_flash_controller *str9xpec_info; - struct arm *armv4_5 = NULL; + struct arm *arm = NULL; struct arm7_9_common *arm7_9 = NULL; struct arm_jtag *jtag_info = NULL; @@ -301,8 +301,8 @@ FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command) /* REVISIT verify that the jtag position of flash controller is * right after *THIS* core, which must be a STR9xx core ... */ - armv4_5 = bank->target->arch_info; - arm7_9 = armv4_5->arch_info; + arm = bank->target->arch_info; + arm7_9 = arm->arch_info; jtag_info = &arm7_9->jtag_info; /* The core is the next tap after the flash controller in the chain */ diff --git a/src/target/arm.h b/src/target/arm.h index 63932e117..86cf4475e 100644 --- a/src/target/arm.h +++ b/src/target/arm.h @@ -197,7 +197,7 @@ struct arm_reg { int num; enum arm_mode mode; struct target *target; - struct arm *armv4_5_common; + struct arm *arm; uint32_t value; }; diff --git a/src/target/arm720t.c b/src/target/arm720t.c index 7a6a05478..94af0f7f8 100644 --- a/src/target/arm720t.c +++ b/src/target/arm720t.c @@ -340,8 +340,7 @@ static int arm720t_soft_reset_halt(struct target *target) struct arm720t_common *arm720t = target_to_arm720(target); struct reg *dbg_stat = &arm720t->arm7_9_common .eice_cache->reg_list[EICE_DBG_STAT]; - struct arm *armv4_5 = &arm720t->arm7_9_common - .armv4_5_common; + struct arm *arm = &arm720t->arm7_9_common.arm; if ((retval = target_halt(target)) != ERROR_OK) { @@ -382,16 +381,16 @@ static int arm720t_soft_reset_halt(struct target *target) /* SVC, ARM state, IRQ and FIQ disabled */ uint32_t cpsr; - cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); cpsr &= ~0xff; cpsr |= 0xd3; - arm_set_cpsr(armv4_5, cpsr); - armv4_5->cpsr->dirty = 1; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = 1; /* start fetching from 0x0 */ - buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = 1; + arm->pc->valid = 1; retval = arm720t_disable_mmu_caches(target, 1, 1, 1); if (retval != ERROR_OK) @@ -428,8 +427,8 @@ static int arm720t_init_arch_info(struct target *target, { struct arm7_9_common *arm7_9 = &arm720t->arm7_9_common; - arm7_9->armv4_5_common.mrc = arm720t_mrc; - arm7_9->armv4_5_common.mcr = arm720t_mcr; + arm7_9->arm.mrc = arm720t_mrc; + arm7_9->arm.mcr = arm720t_mcr; arm7tdmi_init_arch_info(target, arm7_9, tap); @@ -454,7 +453,7 @@ static int arm720t_target_create(struct target *target, Jim_Interp *interp) { struct arm720t_common *arm720t = calloc(1, sizeof(*arm720t)); - arm720t->arm7_9_common.armv4_5_common.is_armv4 = true; + arm720t->arm7_9_common.arm.is_armv4 = true; return arm720t_init_arch_info(target, arm720t, target->tap); } diff --git a/src/target/arm720t.h b/src/target/arm720t.h index f0ab44477..e96f27097 100644 --- a/src/target/arm720t.h +++ b/src/target/arm720t.h @@ -39,7 +39,7 @@ static inline struct arm720t_common * target_to_arm720(struct target *target) { return container_of(target->arch_info, struct arm720t_common, - arm7_9_common.armv4_5_common); + arm7_9_common.arm); } #endif /* ARM720T_H */ diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index ed913024d..a77004e70 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -1043,7 +1043,7 @@ int arm7_9_assert_reset(struct target *target) } target->state = TARGET_RESET; - register_cache_invalidate(arm7_9->armv4_5_common.core_cache); + register_cache_invalidate(arm7_9->arm.core_cache); /* REVISIT why isn't standard debug entry logic sufficient?? */ if (target->reset_halt @@ -1171,7 +1171,7 @@ static int arm7_9_clear_halt(struct target *target) int arm7_9_soft_reset_halt(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int i; @@ -1230,33 +1230,33 @@ int arm7_9_soft_reset_halt(struct target *target) uint32_t r0_thumb, pc_thumb; LOG_DEBUG("target entered debug from Thumb state, changing to ARM"); /* Entered debug from Thumb mode */ - armv4_5->core_state = ARM_STATE_THUMB; + arm->core_state = ARM_STATE_THUMB; arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb); } /* REVISIT likewise for bit 5 -- switch Jazelle-to-ARM */ /* all register content is now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); /* SVC, ARM state, IRQ and FIQ disabled */ uint32_t cpsr; - cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); cpsr &= ~0xff; cpsr |= 0xd3; - arm_set_cpsr(armv4_5, cpsr); - armv4_5->cpsr->dirty = 1; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = 1; /* start fetching from 0x0 */ - buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = 1; + arm->pc->valid = 1; /* reset registers */ for (i = 0; i <= 14; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); buf_set_u32(r->value, 0, 32, 0xffffffff); r->dirty = 1; @@ -1351,7 +1351,7 @@ static int arm7_9_debug_entry(struct target *target) uint32_t cpsr, cpsr_mask = 0; int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; @@ -1392,7 +1392,7 @@ static int arm7_9_debug_entry(struct target *target) { LOG_DEBUG("target entered debug from Thumb state"); /* Entered debug from Thumb mode */ - armv4_5->core_state = ARM_STATE_THUMB; + arm->core_state = ARM_STATE_THUMB; cpsr_mask = 1 << 5; arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb); LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 @@ -1404,13 +1404,13 @@ static int arm7_9_debug_entry(struct target *target) * B.7.3 for the reverse. That'd be the bare minimum... */ LOG_DEBUG("target entered debug from Jazelle state"); - armv4_5->core_state = ARM_STATE_JAZELLE; + arm->core_state = ARM_STATE_JAZELLE; cpsr_mask = 1 << 24; LOG_ERROR("Jazelle debug entry -- BROKEN!"); } else { LOG_DEBUG("target entered debug from ARM state"); /* Entered debug from ARM mode */ - armv4_5->core_state = ARM_STATE_ARM; + arm->core_state = ARM_STATE_ARM; } for (i = 0; i < 16; i++) @@ -1426,9 +1426,9 @@ static int arm7_9_debug_entry(struct target *target) /* Sync our CPSR copy with J or T bits EICE reported, but * which we then erased by putting the core into ARM mode. */ - arm_set_cpsr(armv4_5, cpsr | cpsr_mask); + arm_set_cpsr(arm, cpsr | cpsr_mask); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); @@ -1436,27 +1436,27 @@ static int arm7_9_debug_entry(struct target *target) } LOG_DEBUG("target entered debug state in %s mode", - arm_mode_name(armv4_5->core_mode)); + arm_mode_name(arm->core_mode)); - if (armv4_5->core_state == ARM_STATE_THUMB) + if (arm->core_state == ARM_STATE_THUMB) { LOG_DEBUG("thumb state, applying fixups"); context[0] = r0_thumb; context[15] = pc_thumb; - } else if (armv4_5->core_state == ARM_STATE_ARM) + } else if (arm->core_state == ARM_STATE_ARM) { /* adjust value stored by STM */ context[15] -= 3 * 4; } if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq)) - context[15] -= 3 * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2); + context[15] -= 3 * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2); else - context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARM_STATE_ARM) ? 4 : 2); + context[15] -= arm7_9->dbgreq_adjust_pc * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2); for (i = 0; i <= 15; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]); @@ -1469,16 +1469,16 @@ static int arm7_9_debug_entry(struct target *target) LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]); /* exceptions other than USR & SYS have a saved program status register */ - if (armv4_5->spsr) { + if (arm->spsr) { uint32_t spsr; arm7_9->read_xpsr(target, &spsr, 1); if ((retval = jtag_execute_queue()) != ERROR_OK) { return retval; } - buf_set_u32(armv4_5->spsr->value, 0, 32, spsr); - armv4_5->spsr->dirty = 0; - armv4_5->spsr->valid = 1; + buf_set_u32(arm->spsr->value, 0, 32, spsr); + arm->spsr->dirty = 0; + arm->spsr->valid = 1; } if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1508,7 +1508,7 @@ static int arm7_9_full_context(struct target *target) int i; int retval; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; LOG_DEBUG("-"); @@ -1518,7 +1518,7 @@ static int arm7_9_full_context(struct target *target) return ERROR_TARGET_NOT_HALTED; } - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; @@ -1538,7 +1538,7 @@ static int arm7_9_full_context(struct target *target) */ for (j = 0; j <= 16; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0) + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) valid = 0; } @@ -1547,7 +1547,7 @@ static int arm7_9_full_context(struct target *target) uint32_t tmp_cpsr; /* change processor mode (and mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xe0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; @@ -1555,12 +1555,13 @@ static int arm7_9_full_context(struct target *target) for (j = 0; j < 15; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid == 0) + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0) { - reg_p[j] = (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).value; + reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), j).value; mask |= 1 << j; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).valid = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).dirty = 0; } } @@ -1569,18 +1570,19 @@ static int arm7_9_full_context(struct target *target) arm7_9->read_core_regs(target, mask, reg_p); /* check if the PSR has to be read */ - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid == 0) + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid == 0) { - arm7_9->read_xpsr(target, (uint32_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).value, 1); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; + arm7_9->read_xpsr(target, (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache, + armv4_5_number_to_mode(i), 16).value, 1); + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0; } } } /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) & ~0x20, + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); if ((retval = jtag_execute_queue()) != ERROR_OK) @@ -1605,9 +1607,9 @@ static int arm7_9_full_context(struct target *target) static int arm7_9_restore_context(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *reg; - enum arm_mode current_mode = armv4_5->core_mode; + enum arm_mode current_mode = arm->core_mode; int i, j; int dirty; int mode_change; @@ -1623,7 +1625,7 @@ static int arm7_9_restore_context(struct target *target) if (arm7_9->pre_restore_context) arm7_9->pre_restore_context(target); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; @@ -1635,14 +1637,14 @@ static int arm7_9_restore_context(struct target *target) for (i = 0; i < 6; i++) { LOG_DEBUG("examining %s mode", - arm_mode_name(armv4_5->core_mode)); + arm_mode_name(arm->core_mode)); dirty = 0; mode_change = 0; /* check if there are dirty registers in the current mode */ for (j = 0; j <= 16; j++) { - reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); + reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); if (reg->dirty == 1) { if (reg->valid == 1) @@ -1653,8 +1655,10 @@ static int arm7_9_restore_context(struct target *target) reg_arch_info = reg->arch_info; if ((reg_arch_info->mode != ARM_MODE_ANY) && (reg_arch_info->mode != current_mode) - && !((reg_arch_info->mode == ARM_MODE_USR) && (armv4_5->core_mode == ARM_MODE_SYS)) - && !((reg_arch_info->mode == ARM_MODE_SYS) && (armv4_5->core_mode == ARM_MODE_USR))) + && !((reg_arch_info->mode == ARM_MODE_USR) + && (arm->core_mode == ARM_MODE_SYS)) + && !((reg_arch_info->mode == ARM_MODE_SYS) + && (arm->core_mode == ARM_MODE_USR))) { mode_change = 1; LOG_DEBUG("require mode change"); @@ -1678,7 +1682,7 @@ static int arm7_9_restore_context(struct target *target) uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xe0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; @@ -1688,7 +1692,7 @@ static int arm7_9_restore_context(struct target *target) for (j = 0; j <= 14; j++) { - reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), j); + reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j); if (reg->dirty == 1) { @@ -1699,7 +1703,7 @@ static int arm7_9_restore_context(struct target *target) reg->valid = 1; LOG_DEBUG("writing register %i mode %s " "with value 0x%8.8" PRIx32, j, - arm_mode_name(armv4_5->core_mode), + arm_mode_name(arm->core_mode), regs[j]); } } @@ -1709,7 +1713,7 @@ static int arm7_9_restore_context(struct target *target) arm7_9->write_core_regs(target, mask, regs); } - reg = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_number_to_mode(i), 16); + reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16); struct arm_reg *reg_arch_info; reg_arch_info = reg->arch_info; if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) @@ -1720,34 +1724,32 @@ static int arm7_9_restore_context(struct target *target) } } - if (!armv4_5->cpsr->dirty && (armv4_5->core_mode != current_mode)) - { + if (!arm->cpsr->dirty && (arm->core_mode != current_mode)) { /* restore processor mode (mask T bit) */ uint32_t tmp_cpsr; - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0; + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0; tmp_cpsr |= armv4_5_number_to_mode(i); tmp_cpsr &= ~0x20; LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr)); arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); - } - else if (armv4_5->cpsr->dirty) - { + + } else if (arm->cpsr->dirty) { /* CPSR has been changed, full restore necessary (mask T bit) */ LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); arm7_9->write_xpsr(target, - buf_get_u32(armv4_5->cpsr->value, 0, 32) - & ~0x20, 0); - armv4_5->cpsr->dirty = 0; - armv4_5->cpsr->valid = 1; + buf_get_u32(arm->cpsr->value, 0, 32) + & ~0x20, 0); + arm->cpsr->dirty = 0; + arm->cpsr->valid = 1; } /* restore PC */ LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->pc->value, 0, 32)); - arm7_9->write_pc(target, buf_get_u32(armv4_5->pc->value, 0, 32)); - armv4_5->pc->dirty = 0; + buf_get_u32(arm->pc->value, 0, 32)); + arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32)); + arm->pc->dirty = 0; return ERROR_OK; } @@ -1821,7 +1823,7 @@ static void arm7_9_enable_breakpoints(struct target *target) int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; int err, retval = ERROR_OK; @@ -1840,17 +1842,17 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->pc->value, 0, 32, address); + buf_set_u32(arm->pc->value, 0, 32, address); uint32_t current_pc; - current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) { struct breakpoint *breakpoint; breakpoint = breakpoint_find(target, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); if (breakpoint != NULL) { LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id ); @@ -1875,18 +1877,13 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand target->debug_reason = DBG_REASON_SINGLESTEP; if ((retval = arm7_9_restore_context(target)) != ERROR_OK) - { return retval; - } - if (armv4_5->core_state == ARM_STATE_ARM) + if (arm->core_state == ARM_STATE_ARM) arm7_9->branch_resume(target); - else if (armv4_5->core_state == ARM_STATE_THUMB) - { + else if (arm->core_state == ARM_STATE_THUMB) arm7_9->branch_resume_thumb(target); - } - else - { + else { LOG_ERROR("unhandled core state"); return ERROR_FAIL; } @@ -1912,7 +1909,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand if (retval != ERROR_OK) return retval; LOG_DEBUG("new PC after step: 0x%8.8" PRIx32, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address); if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK) @@ -1927,20 +1924,13 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand arm7_9_enable_watchpoints(target); if ((retval = arm7_9_restore_context(target)) != ERROR_OK) - { return retval; - } - if (armv4_5->core_state == ARM_STATE_ARM) - { + if (arm->core_state == ARM_STATE_ARM) arm7_9->branch_resume(target); - } - else if (armv4_5->core_state == ARM_STATE_THUMB) - { + else if (arm->core_state == ARM_STATE_THUMB) arm7_9->branch_resume_thumb(target); - } - else - { + else { LOG_ERROR("unhandled core state"); return ERROR_FAIL; } @@ -1962,7 +1952,7 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand if (!debug_execution) { /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); target->state = TARGET_RUNNING; if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK) { @@ -1986,9 +1976,9 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; uint32_t current_pc; - current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); if (next_pc != current_pc) { @@ -2038,7 +2028,7 @@ void arm7_9_disable_eice_step(struct target *target) int arm7_9_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct breakpoint *breakpoint = NULL; int err, retval; @@ -2050,9 +2040,9 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->pc->value, 0, 32, address); + buf_set_u32(arm->pc->value, 0, 32, address); - uint32_t current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + uint32_t current_pc = buf_get_u32(arm->pc->value, 0, 32); /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) @@ -2076,22 +2066,15 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle } if ((retval = arm7_9_restore_context(target)) != ERROR_OK) - { return retval; - } arm7_9->enable_single_step(target, next_pc); - if (armv4_5->core_state == ARM_STATE_ARM) - { + if (arm->core_state == ARM_STATE_ARM) arm7_9->branch_resume(target); - } - else if (armv4_5->core_state == ARM_STATE_THUMB) - { + else if (arm->core_state == ARM_STATE_THUMB) arm7_9->branch_resume_thumb(target); - } - else - { + else { LOG_ERROR("unhandled core state"); return ERROR_FAIL; } @@ -2105,7 +2088,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle arm7_9->disable_single_step(target); /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); if (err != ERROR_OK) { @@ -2137,21 +2120,21 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, int retval; struct arm_reg *areg = r->arch_info; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; if ((num < 0) || (num > 16)) return ERROR_COMMAND_SYNTAX_ERROR; if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0; + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0; tmp_cpsr |= mode; tmp_cpsr &= ~0x20; arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); @@ -2183,11 +2166,11 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r, buf_set_u32(r->value, 0, 32, value); if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); } @@ -2200,20 +2183,20 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, uint32_t reg[16]; struct arm_reg *areg = r->arch_info; struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; if ((num < 0) || (num > 16)) return ERROR_COMMAND_SYNTAX_ERROR; if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { uint32_t tmp_cpsr; /* change processor mode (mask T bit) */ - tmp_cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 8) & 0xE0; + tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8) & 0xE0; tmp_cpsr |= mode; tmp_cpsr &= ~0x20; arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0); @@ -2244,11 +2227,11 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, r->dirty = 0; if ((mode != ARM_MODE_ANY) - && (mode != armv4_5->core_mode) + && (mode != arm->core_mode) && (areg->mode != ARM_MODE_ANY)) { /* restore processor mode (mask T bit) */ arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); } @@ -2258,7 +2241,7 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r, int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; uint32_t reg[16]; uint32_t num_accesses = 0; int thisrun_accesses; @@ -2401,11 +2384,11 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u break; } - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; for (i = 0; i <= last_reg; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); r->dirty = r->valid; } @@ -2417,12 +2400,12 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u return ERROR_TARGET_DATA_ABORT; } - if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT)) + if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); return ERROR_TARGET_DATA_ABORT; @@ -2434,7 +2417,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; uint32_t reg[16]; @@ -2624,11 +2607,11 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1); embeddedice_store_reg(dbg_ctrl); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) return ERROR_FAIL; for (i = 0; i <= last_reg; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); r->dirty = r->valid; } @@ -2640,12 +2623,12 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, return ERROR_TARGET_DATA_ABORT; } - if (((cpsr & 0x1f) == ARM_MODE_ABT) && (armv4_5->core_mode != ARM_MODE_ABT)) + if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) { LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count); arm7_9->write_xpsr_im8(target, - buf_get_u32(armv4_5->cpsr->value, 0, 8) + buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0); return ERROR_TARGET_DATA_ABORT; @@ -2806,10 +2789,10 @@ int arm7_9_examine(struct target *target) (*cache_p) = t; arm7_9->eice_cache = (*cache_p); - if (arm7_9->armv4_5_common.etm) + if (arm7_9->arm.etm) (*cache_p)->next = etm_build_reg_cache(target, &arm7_9->jtag_info, - arm7_9->armv4_5_common.etm); + arm7_9->arm.etm); target_set_examined(target); } @@ -2817,7 +2800,7 @@ int arm7_9_examine(struct target *target) retval = embeddedice_setup(target); if (retval == ERROR_OK) retval = arm7_9_setup(target); - if (retval == ERROR_OK && arm7_9->armv4_5_common.etm) + if (retval == ERROR_OK && arm7_9->arm.etm) retval = etm_setup(target); return retval; } @@ -2934,7 +2917,7 @@ static int arm7_9_setup_semihosting(struct target *target, int enable) int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) { int retval = ERROR_OK; - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; arm7_9->common_magic = ARM7_9_COMMON_MAGIC; @@ -2948,13 +2931,13 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9) arm7_9->fast_memory_access = false; arm7_9->dcc_downloads = false; - armv4_5->arch_info = arm7_9; - armv4_5->read_core_reg = arm7_9_read_core_reg; - armv4_5->write_core_reg = arm7_9_write_core_reg; - armv4_5->full_context = arm7_9_full_context; - armv4_5->setup_semihosting = arm7_9_setup_semihosting; + arm->arch_info = arm7_9; + arm->read_core_reg = arm7_9_read_core_reg; + arm->write_core_reg = arm7_9_write_core_reg; + arm->full_context = arm7_9_full_context; + arm->setup_semihosting = arm7_9_setup_semihosting; - retval = arm_init_arch_info(target, armv4_5); + retval = arm_init_arch_info(target, arm); if (retval != ERROR_OK) return retval; diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h index 780d6c9a3..536f56177 100644 --- a/src/target/arm7_9_common.h +++ b/src/target/arm7_9_common.h @@ -39,7 +39,7 @@ */ struct arm7_9_common { - struct arm armv4_5_common; + struct arm arm; uint32_t common_magic; struct arm_jtag jtag_info; /**< JTAG information for target */ @@ -109,7 +109,7 @@ static inline struct arm7_9_common * target_to_arm7_9(struct target *target) { return container_of(target->arch_info, struct arm7_9_common, - armv4_5_common); + arm); } static inline bool is_arm7_9(struct arm7_9_common *arm7_9) diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 3ede36cc9..d39ef3ffc 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -586,7 +586,7 @@ static void arm7tdmi_branch_resume(struct target *target) static void arm7tdmi_branch_resume_thumb(struct target *target) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; @@ -603,7 +603,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target) arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */ arm7tdmi_clock_out(jtag_info, - buf_get_u32(armv4_5->pc->value, 0, 32) | 1, NULL, 0); + buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0); @@ -631,7 +631,7 @@ static void arm7tdmi_branch_resume_thumb(struct target *target) /* fetch NOP, LDR in Execute */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */ - arm7tdmi_clock_out(jtag_info, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); + arm7tdmi_clock_out(jtag_info, buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0); /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ arm7tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, NULL, 0); @@ -647,9 +647,9 @@ static void arm7tdmi_branch_resume_thumb(struct target *target) static void arm7tdmi_build_reg_cache(struct target *target) { struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); - (*cache_p) = arm_build_reg_cache(target, armv4_5); + (*cache_p) = arm_build_reg_cache(target, arm); } int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target) @@ -713,7 +713,7 @@ static int arm7tdmi_target_create(struct target *target, Jim_Interp *interp) arm7_9 = calloc(1,sizeof(struct arm7_9_common)); arm7tdmi_init_arch_info(target, arm7_9, target->tap); - arm7_9->armv4_5_common.is_armv4 = true; + arm7_9->arm.is_armv4 = true; return ERROR_OK; } diff --git a/src/target/arm920t.c b/src/target/arm920t.c index ecc158c75..055e46f8f 100644 --- a/src/target/arm920t.c +++ b/src/target/arm920t.c @@ -246,11 +246,11 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode, static int arm920t_read_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t address, uint32_t *value) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); uint32_t* regs_p[1]; uint32_t regs[2]; uint32_t cp15c15 = 0x0; - struct reg *r = armv4_5->core_cache->reg_list; + struct reg *r = arm->core_cache->reg_list; /* load address into R1 */ regs[1] = address; @@ -280,7 +280,7 @@ static int arm920t_read_cp15_interpreted(struct target *target, cp15_opcode, address, *value); #endif - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; @@ -297,9 +297,9 @@ int arm920t_write_cp15_interpreted(struct target *target, uint32_t cp15_opcode, uint32_t value, uint32_t address) { uint32_t cp15c15 = 0x0; - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); uint32_t regs[2]; - struct reg *r = armv4_5->core_cache->reg_list; + struct reg *r = arm->core_cache->reg_list; /* load value, address into R0, R1 */ regs[0] = value; @@ -325,7 +325,7 @@ int arm920t_write_cp15_interpreted(struct target *target, cp15_opcode, value, address); #endif - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; @@ -763,7 +763,7 @@ int arm920t_soft_reset_halt(struct target *target) int retval = ERROR_OK; struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) @@ -807,16 +807,16 @@ int arm920t_soft_reset_halt(struct target *target) /* SVC, ARM state, IRQ and FIQ disabled */ uint32_t cpsr; - cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); cpsr &= ~0xff; cpsr |= 0xd3; - arm_set_cpsr(armv4_5, cpsr); - armv4_5->cpsr->dirty = 1; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = 1; /* start fetching from 0x0 */ - buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = 1; + arm->pc->valid = 1; arm920t_disable_mmu_caches(target, 1, 1, 1); arm920t->armv4_5_mmu.mmu_enabled = 0; @@ -841,8 +841,8 @@ static int arm920t_init_arch_info(struct target *target, { struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; - arm7_9->armv4_5_common.mrc = arm920t_mrc; - arm7_9->armv4_5_common.mcr = arm920t_mcr; + arm7_9->arm.mrc = arm920t_mrc; + arm7_9->arm.mcr = arm920t_mcr; /* initialize arm7/arm9 specific info (including armv4_5) */ arm9tdmi_init_arch_info(target, arm7_9, tap); @@ -887,7 +887,7 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -1148,14 +1148,14 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) fclose(output); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } /* force writeback of the valid data */ - r = armv4_5->core_cache->reg_list; + r = arm->core_cache->reg_list; r[0].dirty = r[0].valid; r[1].dirty = r[1].valid; r[2].dirty = r[2].valid; @@ -1165,10 +1165,10 @@ COMMAND_HANDLER(arm920t_handle_read_cache_command) r[6].dirty = r[6].valid; r[7].dirty = r[7].valid; - r = arm_reg_current(armv4_5, 8); + r = arm_reg_current(arm, 8); r->dirty = r->valid; - r = arm_reg_current(armv4_5, 9); + r = arm_reg_current(arm, 9); r->dirty = r->valid; return ERROR_OK; @@ -1180,7 +1180,7 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) struct target *target = get_current_target(CMD_CTX); struct arm920t_common *arm920t = target_to_arm920(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; uint32_t cp15c15; uint32_t cp15_ctrl, cp15_ctrl_saved; uint32_t regs[16]; @@ -1477,14 +1477,14 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) fclose(output); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } /* force writeback of the valid data */ - r = armv4_5->core_cache->reg_list; + r = arm->core_cache->reg_list; r[0].dirty = r[0].valid; r[1].dirty = r[1].valid; r[2].dirty = r[2].valid; @@ -1494,10 +1494,10 @@ COMMAND_HANDLER(arm920t_handle_read_mmu_command) r[6].dirty = r[6].valid; r[7].dirty = r[7].valid; - r = arm_reg_current(armv4_5, 8); + r = arm_reg_current(arm, 8); r->dirty = r->valid; - r = arm_reg_current(armv4_5, 9); + r = arm_reg_current(arm, 9); r->dirty = r->valid; return ERROR_OK; diff --git a/src/target/arm920t.h b/src/target/arm920t.h index f4c852be8..0cefd1e67 100644 --- a/src/target/arm920t.h +++ b/src/target/arm920t.h @@ -42,7 +42,7 @@ static inline struct arm920t_common * target_to_arm920(struct target *target) { return container_of(target->arch_info, struct arm920t_common, - arm7_9_common.armv4_5_common); + arm7_9_common.arm); } struct arm920t_cache_line diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 47b94d179..aaf4021af 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -557,7 +557,7 @@ int arm926ejs_soft_reset_halt(struct target *target) int retval = ERROR_OK; struct arm926ejs_common *arm926ejs = target_to_arm926(target); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; if ((retval = target_halt(target)) != ERROR_OK) @@ -600,16 +600,16 @@ int arm926ejs_soft_reset_halt(struct target *target) /* SVC, ARM state, IRQ and FIQ disabled */ uint32_t cpsr; - cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); cpsr &= ~0xff; cpsr |= 0xd3; - arm_set_cpsr(armv4_5, cpsr); - armv4_5->cpsr->dirty = 1; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = 1; /* start fetching from 0x0 */ - buf_set_u32(armv4_5->pc->value, 0, 32, 0x0); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, 0x0); + arm->pc->dirty = 1; + arm->pc->valid = 1; retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1); if (retval != ERROR_OK) @@ -713,8 +713,8 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm { struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common; - arm7_9->armv4_5_common.mrc = arm926ejs_mrc; - arm7_9->armv4_5_common.mcr = arm926ejs_mcr; + arm7_9->arm.mrc = arm926ejs_mrc; + arm7_9->arm.mcr = arm926ejs_mcr; /* initialize arm7/arm9 specific info (including armv4_5) */ arm9tdmi_init_arch_info(target, arm7_9, tap); diff --git a/src/target/arm926ejs.h b/src/target/arm926ejs.h index 76cc24a0c..e2a53a6b0 100644 --- a/src/target/arm926ejs.h +++ b/src/target/arm926ejs.h @@ -42,7 +42,7 @@ static inline struct arm926ejs_common * target_to_arm926(struct target *target) { return container_of(target->arch_info, struct arm926ejs_common, - arm7_9_common.armv4_5_common); + arm7_9_common.arm); } diff --git a/src/target/arm946e.h b/src/target/arm946e.h index 557674e3a..ce0ead9f8 100644 --- a/src/target/arm946e.h +++ b/src/target/arm946e.h @@ -41,7 +41,7 @@ static inline struct arm946e_common * target_to_arm946(struct target *target) { return container_of(target->arch_info, struct arm946e_common, - arm7_9_common.armv4_5_common); + arm7_9_common.arm); } int arm946e_init_arch_info(struct target *target, diff --git a/src/target/arm966e.h b/src/target/arm966e.h index 24dcec306..cfd80d2d5 100644 --- a/src/target/arm966e.h +++ b/src/target/arm966e.h @@ -38,7 +38,7 @@ static inline struct arm966e_common * target_to_arm966(struct target *target) { return container_of(target->arch_info, struct arm966e_common, - arm7_9_common.armv4_5_common); + arm7_9_common.arm); } int arm966e_init_arch_info(struct target *target, diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 493adb3bf..b3cd359dc 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -658,7 +658,7 @@ static void arm9tdmi_branch_resume_thumb(struct target *target) LOG_DEBUG("-"); struct arm7_9_common *arm7_9 = target_to_arm7_9(target); - struct arm *armv4_5 = &arm7_9->armv4_5_common; + struct arm *arm = &arm7_9->arm; struct arm_jtag *jtag_info = &arm7_9->jtag_info; struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT]; @@ -673,7 +673,7 @@ static void arm9tdmi_branch_resume_thumb(struct target *target) arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (2nd cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, - buf_get_u32(armv4_5->pc->value, 0, 32) | 1, NULL, 0); + buf_get_u32(arm->pc->value, 0, 32) | 1, NULL, 0); /* nothing fetched, LDM in EXECUTE stage (3rd cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -700,7 +700,8 @@ static void arm9tdmi_branch_resume_thumb(struct target *target) /* fetch NOP, LDR in Execute */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); /* nothing fetched, LDR in EXECUTE stage (2nd cycle) */ - arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32), NULL, 0); + arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, + buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32), NULL, 0); /* nothing fetched, LDR in EXECUTE stage (3rd cycle) */ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0); @@ -746,9 +747,9 @@ void arm9tdmi_disable_single_step(struct target *target) static void arm9tdmi_build_reg_cache(struct target *target) { struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); - (*cache_p) = arm_build_reg_cache(target, armv4_5); + (*cache_p) = arm_build_reg_cache(target, arm); } int arm9tdmi_init_target(struct command_context *cmd_ctx, @@ -817,7 +818,7 @@ static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp) struct arm7_9_common *arm7_9 = calloc(1,sizeof(struct arm7_9_common)); arm9tdmi_init_arch_info(target, arm7_9, target->tap); - arm7_9->armv4_5_common.is_armv4 = true; + arm7_9->arm.is_armv4 = true; return ERROR_OK; } diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 1723b438d..a0ffdde5e 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -781,71 +781,71 @@ static int arm_simulate_step_core(struct target *target, static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32); + return buf_get_u32(arm->core_cache->reg_list[reg].value, 0, 32); } static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value); + buf_set_u32(arm->core_cache->reg_list[reg].value, 0, 32, value); } static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, reg).value, 0, 32); + return buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, + arm->core_mode, reg).value, 0, 32); } static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, - armv4_5->core_mode, reg).value, 0, 32, value); + buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, + arm->core_mode, reg).value, 0, 32, value); } static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - return buf_get_u32(armv4_5->cpsr->value, pos, bits); + return buf_get_u32(arm->cpsr->value, pos, bits); } static enum arm_state armv4_5_get_state(struct arm_sim_interface *sim) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - return armv4_5->core_state; + return arm->core_state; } static void armv4_5_set_state(struct arm_sim_interface *sim, enum arm_state mode) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - armv4_5->core_state = mode; + arm->core_state = mode; } static enum arm_mode armv4_5_get_mode(struct arm_sim_interface *sim) { - struct arm *armv4_5 = (struct arm *)sim->user_data; + struct arm *arm = (struct arm *)sim->user_data; - return armv4_5->core_mode; + return arm->core_mode; } int arm_simulate_step(struct target *target, uint32_t *dry_run_pc) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); struct arm_sim_interface sim; - sim.user_data = armv4_5; + sim.user_data = arm; sim.get_reg = &armv4_5_get_reg; sim.set_reg = &armv4_5_set_reg; sim.get_reg_mode = &armv4_5_get_reg_mode; diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 3e3fea03c..949ced410 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -470,8 +470,8 @@ static void arm_gdb_dummy_init(void) static int armv4_5_get_core_reg(struct reg *reg) { int retval; - struct arm_reg *armv4_5 = reg->arch_info; - struct target *target = armv4_5->target; + struct arm_reg *reg_arch_info = reg->arch_info; + struct target *target = reg_arch_info->target; if (target->state != TARGET_HALTED) { @@ -479,7 +479,8 @@ static int armv4_5_get_core_reg(struct reg *reg) return ERROR_TARGET_NOT_HALTED; } - retval = armv4_5->armv4_5_common->read_core_reg(target, reg, armv4_5->num, armv4_5->mode); + retval = reg_arch_info->arm->read_core_reg(target, reg, + reg_arch_info->num, reg_arch_info->mode); if (retval == ERROR_OK) { reg->valid = 1; reg->dirty = 0; @@ -490,8 +491,8 @@ static int armv4_5_get_core_reg(struct reg *reg) static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf) { - struct arm_reg *armv4_5 = reg->arch_info; - struct target *target = armv4_5->target; + struct arm_reg *reg_arch_info = reg->arch_info; + struct target *target = reg_arch_info->target; struct arm *armv4_5_target = target_to_arm(target); uint32_t value = buf_get_u32(buf, 0, 32); @@ -539,13 +540,13 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) int num_regs = ARRAY_SIZE(arm_core_regs); struct reg_cache *cache = malloc(sizeof(struct reg_cache)); struct reg *reg_list = calloc(num_regs, sizeof(struct reg)); - struct arm_reg *arch_info = calloc(num_regs, sizeof(struct arm_reg)); + struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg)); int i; - if (!cache || !reg_list || !arch_info) { + if (!cache || !reg_list || !reg_arch_info) { free(cache); free(reg_list); - free(arch_info); + free(reg_arch_info); return NULL; } @@ -563,16 +564,16 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) /* REVISIT handle Cortex-M, which only shadows R13/SP */ - arch_info[i].num = arm_core_regs[i].cookie; - arch_info[i].mode = arm_core_regs[i].mode; - arch_info[i].target = target; - arch_info[i].armv4_5_common = arm; + reg_arch_info[i].num = arm_core_regs[i].cookie; + reg_arch_info[i].mode = arm_core_regs[i].mode; + reg_arch_info[i].target = target; + reg_arch_info[i].arm = arm; reg_list[i].name = (char *) arm_core_regs[i].name; reg_list[i].size = 32; - reg_list[i].value = &arch_info[i].value; + reg_list[i].value = ®_arch_info[i].value; reg_list[i].type = &arm_reg_type; - reg_list[i].arch_info = &arch_info[i]; + reg_list[i].arch_info = ®_arch_info[i]; cache->num_regs++; } @@ -585,9 +586,9 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm) int arm_arch_state(struct target *target) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); - if (armv4_5->common_magic != ARM_COMMON_MAGIC) + if (arm->common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARM target"); return ERROR_FAIL; @@ -595,12 +596,12 @@ int arm_arch_state(struct target *target) LOG_USER("target halted in %s state due to %s, current mode: %s\n" "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s", - arm_state_strings[armv4_5->core_state], + arm_state_strings[arm->core_state], debug_reason_name(target), - arm_mode_name(armv4_5->core_mode), - buf_get_u32(armv4_5->cpsr->value, 0, 32), - buf_get_u32(armv4_5->pc->value, 0, 32), - armv4_5->is_semihosting ? ", semihosting" : ""); + arm_mode_name(arm->core_mode), + buf_get_u32(arm->cpsr->value, 0, 32), + buf_get_u32(arm->pc->value, 0, 32), + arm->is_semihosting ? ", semihosting" : ""); return ERROR_OK; } @@ -611,10 +612,10 @@ int arm_arch_state(struct target *target) COMMAND_HANDLER(handle_armv4_5_reg_command) { struct target *target = get_current_target(CMD_CTX); - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); struct reg *regs; - if (!is_arm(armv4_5)) + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; @@ -626,25 +627,25 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) return ERROR_FAIL; } - if (armv4_5->core_type != ARM_MODE_ANY) + if (arm->core_type != ARM_MODE_ANY) { command_print(CMD_CTX, "Microcontroller Profile not supported - use standard reg cmd"); return ERROR_OK; } - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } - if (!armv4_5->full_context) { + if (!arm->full_context) { command_print(CMD_CTX, "error: target doesn't support %s", CMD_NAME); return ERROR_FAIL; } - regs = armv4_5->core_cache->reg_list; + regs = arm->core_cache->reg_list; for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) { const char *name; @@ -660,7 +661,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) sep = ""; break; case ARM_MODE_MON: - if (armv4_5->core_type != ARM_MODE_MON) + if (arm->core_type != ARM_MODE_MON) continue; /* FALLTHROUGH */ default: @@ -687,7 +688,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) /* REVISIT be smarter about faults... */ if (!reg->valid) - armv4_5->full_context(target); + arm->full_context(target); value = buf_get_u32(reg->value, 0, 32); output_len += snprintf(output + output_len, @@ -705,15 +706,15 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) COMMAND_HANDLER(handle_armv4_5_core_state_command) { struct target *target = get_current_target(CMD_CTX); - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); - if (!is_arm(armv4_5)) + if (!is_arm(arm)) { command_print(CMD_CTX, "current target isn't an ARM"); return ERROR_FAIL; } - if (armv4_5->core_type == ARM_MODE_THREAD) + if (arm->core_type == ARM_MODE_THREAD) { /* armv7m not supported */ command_print(CMD_CTX, "Unsupported Command"); @@ -724,15 +725,15 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command) { if (strcmp(CMD_ARGV[0], "arm") == 0) { - armv4_5->core_state = ARM_STATE_ARM; + arm->core_state = ARM_STATE_ARM; } if (strcmp(CMD_ARGV[0], "thumb") == 0) { - armv4_5->core_state = ARM_STATE_THUMB; + arm->core_state = ARM_STATE_THUMB; } } - command_print(CMD_CTX, "core state: %s", arm_state_strings[armv4_5->core_state]); + command_print(CMD_CTX, "core state: %s", arm_state_strings[arm->core_state]); return ERROR_OK; } @@ -1056,10 +1057,10 @@ const struct command_registration arm_command_handlers[] = { int arm_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); int i; - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; @@ -1069,13 +1070,13 @@ int arm_get_gdb_reg_list(struct target *target, *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size)); for (i = 0; i < 16; i++) - (*reg_list)[i] = arm_reg_current(armv4_5, i); + (*reg_list)[i] = arm_reg_current(arm, i); for (i = 16; i < 24; i++) (*reg_list)[i] = &arm_gdb_dummy_fp_reg; (*reg_list)[24] = &arm_gdb_dummy_fps_reg; - (*reg_list)[25] = armv4_5->cpsr; + (*reg_list)[25] = arm->cpsr; return ERROR_OK; } @@ -1084,7 +1085,7 @@ int arm_get_gdb_reg_list(struct target *target, static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info) { int retval; - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); if ((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK) { @@ -1102,10 +1103,10 @@ static int armv4_5_run_algorithm_completion(struct target *target, uint32_t exit } /* fast exit: ARMv5+ code can use BKPT */ - if (exit_point && buf_get_u32(armv4_5->pc->value, 0, 32) != exit_point) + if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) { LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "", - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); return ERROR_TARGET_TIMEOUT; } @@ -1120,9 +1121,9 @@ int armv4_5_run_algorithm_inner(struct target *target, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); struct arm_algorithm *arm_algorithm_info = arch_info; - enum arm_state core_state = armv4_5->core_state; + enum arm_state core_state = arm->core_state; uint32_t context[17]; uint32_t cpsr; int exit_breakpoint_size = 0; @@ -1143,14 +1144,14 @@ int armv4_5_run_algorithm_inner(struct target *target, return ERROR_TARGET_NOT_HALTED; } - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { LOG_ERROR("not a valid arm core mode - communication failure?"); return ERROR_FAIL; } /* armv5 and later can terminate with BKPT instruction; less overhead */ - if (!exit_point && armv4_5->is_armv4) + if (!exit_point && arm->is_armv4) { LOG_ERROR("ARMv4 target needs HW breakpoint location"); return ERROR_FAIL; @@ -1163,14 +1164,14 @@ int armv4_5_run_algorithm_inner(struct target *target, { struct reg *r; - r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + r = &ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i); if (!r->valid) - armv4_5->read_core_reg(target, r, i, + arm->read_core_reg(target, r, i, arm_algorithm_info->core_mode); context[i] = buf_get_u32(r->value, 0, 32); } - cpsr = buf_get_u32(armv4_5->cpsr->value, 0, 32); + cpsr = buf_get_u32(arm->cpsr->value, 0, 32); for (i = 0; i < num_mem_params; i++) { @@ -1182,7 +1183,7 @@ int armv4_5_run_algorithm_inner(struct target *target, for (i = 0; i < num_reg_params; i++) { - struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -1201,10 +1202,10 @@ int armv4_5_run_algorithm_inner(struct target *target, } } - armv4_5->core_state = arm_algorithm_info->core_state; - if (armv4_5->core_state == ARM_STATE_ARM) + arm->core_state = arm_algorithm_info->core_state; + if (arm->core_state == ARM_STATE_ARM) exit_breakpoint_size = 4; - else if (armv4_5->core_state == ARM_STATE_THUMB) + else if (arm->core_state == ARM_STATE_THUMB) exit_breakpoint_size = 2; else { @@ -1216,10 +1217,10 @@ int armv4_5_run_algorithm_inner(struct target *target, { LOG_DEBUG("setting core_mode: 0x%2.2x", arm_algorithm_info->core_mode); - buf_set_u32(armv4_5->cpsr->value, 0, 5, + buf_set_u32(arm->cpsr->value, 0, 5, arm_algorithm_info->core_mode); - armv4_5->cpsr->dirty = 1; - armv4_5->cpsr->valid = 1; + arm->cpsr->dirty = 1; + arm->cpsr->valid = 1; } /* terminate using a hardware or (ARMv5+) software breakpoint */ @@ -1257,7 +1258,7 @@ int armv4_5_run_algorithm_inner(struct target *target, if (reg_params[i].direction != PARAM_OUT) { - struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0); + struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0); if (!reg) { LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name); @@ -1280,20 +1281,24 @@ int armv4_5_run_algorithm_inner(struct target *target, for (i = 0; i <= 16; i++) { uint32_t regvalue; - regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32); + regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, + arm_algorithm_info->core_mode, i).value, 0, 32); if (regvalue != context[i]) { - LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).name, context[i]); - buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).value, 0, 32, context[i]); - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).valid = 1; - ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, arm_algorithm_info->core_mode, i).dirty = 1; + LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", + ARMV4_5_CORE_REG_MODE(arm->core_cache, + arm_algorithm_info->core_mode, i).name, context[i]); + buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache, + arm_algorithm_info->core_mode, i).value, 0, 32, context[i]); + ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).valid = 1; + ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode, i).dirty = 1; } } - arm_set_cpsr(armv4_5, cpsr); - armv4_5->cpsr->dirty = 1; + arm_set_cpsr(arm, cpsr); + arm->cpsr->dirty = 1; - armv4_5->core_state = core_state; + arm->core_state = core_state; return retval; } @@ -1312,7 +1317,7 @@ int arm_checksum_memory(struct target *target, { struct working_area *crc_algorithm; struct arm_algorithm armv4_5_info; - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); struct reg_param reg_params[2]; int retval; uint32_t i; @@ -1377,7 +1382,7 @@ int arm_checksum_memory(struct target *target, int timeout = 20000 * (1 + (count / (1024 * 1024))); /* armv4 must exit using a hardware breakpoint */ - if (armv4_5->is_armv4) + if (arm->is_armv4) exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8; retval = target_run_algorithm(target, 0, NULL, 2, reg_params, @@ -1414,7 +1419,7 @@ int arm_blank_check_memory(struct target *target, struct working_area *check_algorithm; struct reg_param reg_params[3]; struct arm_algorithm armv4_5_info; - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); int retval; uint32_t i; uint32_t exit_var = 0; @@ -1459,7 +1464,7 @@ int arm_blank_check_memory(struct target *target, buf_set_u32(reg_params[2].value, 0, 32, 0xff); /* armv4 must exit using a hardware breakpoint */ - if (armv4_5->is_armv4) + if (arm->is_armv4) exit_var = check_algorithm->address + sizeof(check_code) - 4; retval = target_run_algorithm(target, 0, NULL, 3, reg_params, @@ -1487,9 +1492,9 @@ int arm_blank_check_memory(struct target *target, static int arm_full_context(struct target *target) { - struct arm *armv4_5 = target_to_arm(target); - unsigned num_regs = armv4_5->core_cache->num_regs; - struct reg *reg = armv4_5->core_cache->reg_list; + struct arm *arm = target_to_arm(target); + unsigned num_regs = arm->core_cache->num_regs; + struct reg *reg = arm->core_cache->reg_list; int retval = ERROR_OK; for (; num_regs && retval == ERROR_OK; num_regs--, reg++) { @@ -1518,27 +1523,27 @@ static int arm_default_mcr(struct target *target, int cpnum, return ERROR_FAIL; } -int arm_init_arch_info(struct target *target, struct arm *armv4_5) +int arm_init_arch_info(struct target *target, struct arm *arm) { - target->arch_info = armv4_5; - armv4_5->target = target; + target->arch_info = arm; + arm->target = target; - armv4_5->common_magic = ARM_COMMON_MAGIC; + arm->common_magic = ARM_COMMON_MAGIC; /* core_type may be overridden by subtype logic */ - if (armv4_5->core_type != ARM_MODE_THREAD) { - armv4_5->core_type = ARM_MODE_ANY; - arm_set_cpsr(armv4_5, ARM_MODE_USR); + if (arm->core_type != ARM_MODE_THREAD) { + arm->core_type = ARM_MODE_ANY; + arm_set_cpsr(arm, ARM_MODE_USR); } /* default full_context() has no core-specific optimizations */ - if (!armv4_5->full_context && armv4_5->read_core_reg) - armv4_5->full_context = arm_full_context; + if (!arm->full_context && arm->read_core_reg) + arm->full_context = arm_full_context; - if (!armv4_5->mrc) - armv4_5->mrc = arm_default_mrc; - if (!armv4_5->mcr) - armv4_5->mcr = arm_default_mcr; + if (!arm->mrc) + arm->mrc = arm_default_mrc; + if (!arm->mcr) + arm->mcr = arm_default_mcr; return ERROR_OK; } diff --git a/src/target/armv7a.c b/src/target/armv7a.c index 13dca9ae3..2ef370b9b 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -43,7 +43,7 @@ static void armv7a_show_fault_registers(struct target *target) { uint32_t dfsr, ifsr, dfar, ifar; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; int retval; retval = dpm->prepare(dpm); @@ -90,7 +90,7 @@ done: static int armv7a_read_ttbcr(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t ttbcr; int retval = dpm->prepare(dpm); if (retval!=ERROR_OK) goto done; @@ -130,7 +130,7 @@ int armv7a_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val) uint32_t second_lvl_descriptor = 0x0; int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t ttb = 0; /* default ttb0 */ if (armv7a->armv7a_mmu.ttbr1_used == -1) armv7a_read_ttbcr(target); if ((armv7a->armv7a_mmu.ttbr1_used) && @@ -238,7 +238,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, { int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t virt = va & ~0xfff; uint32_t NOS,NS,INNER,OUTER; *val = 0xdeadbeef; @@ -332,7 +332,7 @@ static int armv7a_handle_inner_cache_info_command(struct command_context *cmd_ct static int _armv7a_flush_all_data(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; struct armv7a_cachesize *d_u_size = &(armv7a->armv7a_mmu.armv7a_cache.d_u_size); int32_t c_way, c_index = d_u_size->index; @@ -546,7 +546,7 @@ static int armv7a_read_mpidr(struct target *target) { int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t mpidr; retval = dpm->prepare(dpm); if (retval!=ERROR_OK) goto done; @@ -583,7 +583,7 @@ int armv7a_identify_cache(struct target *target) /* read cache descriptor */ int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; uint32_t cache_selected,clidr; uint32_t cache_i_reg, cache_d_reg; struct armv7a_cache_common *cache = &(armv7a->armv7a_mmu.armv7a_cache); @@ -612,7 +612,7 @@ int armv7a_identify_cache(struct target *target) &cache_selected); if (retval!=ERROR_OK) goto done; - retval = armv7a->armv4_5_common.mrc(target, 15, + retval = armv7a->arm.mrc(target, 15, 2, 0, /* op1, op2 */ 0, 0, /* CRn, CRm */ &cache_selected); @@ -721,12 +721,12 @@ done: int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a) { - struct arm *armv4_5 = &armv7a->armv4_5_common; - armv4_5->arch_info = armv7a; - target->arch_info = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; + arm->arch_info = armv7a; + target->arch_info = &armv7a->arm; /* target is useful in all function arm v4 5 compatible */ - armv7a->armv4_5_common.target = target; - armv7a->armv4_5_common.common_magic = ARM_COMMON_MAGIC; + armv7a->arm.target = target; + armv7a->arm.common_magic = ARM_COMMON_MAGIC; armv7a->common_magic = ARMV7_COMMON_MAGIC; armv7a->armv7a_mmu.armv7a_cache.l2_cache = NULL; armv7a->armv7a_mmu.armv7a_cache.ctype = -1; @@ -743,7 +743,7 @@ int armv7a_arch_state(struct target *target) }; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; if (armv7a->common_magic != ARMV7_COMMON_MAGIC) { @@ -758,7 +758,7 @@ int armv7a_arch_state(struct target *target) state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled], state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]); - if (armv4_5->core_mode == ARM_MODE_ABT) + if (arm->core_mode == ARM_MODE_ABT) armv7a_show_fault_registers(target); if (target->debug_reason == DBG_REASON_WATCHPOINT) LOG_USER("Watchpoint triggered at PC %#08x", diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 6f54ce6b8..bfc0e7067 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -96,7 +96,7 @@ struct armv7a_mmu_common struct armv7a_common { - struct arm armv4_5_common; + struct arm arm; int common_magic; struct reg_cache *core_cache; @@ -125,7 +125,7 @@ static inline struct armv7a_common * target_to_armv7a(struct target *target) { return container_of(target->arch_info, struct armv7a_common, - armv4_5_common); + arm); } /* register offsets from armv7a.debug_base */ diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index c9401af7d..862fd554f 100755 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -87,7 +87,7 @@ static int cortex_a8_restore_cp15_control_reg(struct target* target) { cortex_a8->cp15_control_reg_curr = cortex_a8->cp15_control_reg; //LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg); - retval = armv7a->armv4_5_common.mcr(target, 15, + retval = armv7a->arm.mcr(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg); @@ -103,22 +103,22 @@ static int cortex_a8_check_address(struct target *target, uint32_t address) struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); uint32_t os_border = armv7a->armv7a_mmu.os_border; if ((address < os_border) && - (armv7a->armv4_5_common.core_mode == ARM_MODE_SVC)){ + (armv7a->arm.core_mode == ARM_MODE_SVC)) { LOG_ERROR("%x access in userspace and target in supervisor",address); return ERROR_FAIL; } if ((address >= os_border) && - ( cortex_a8->curr_mode != ARM_MODE_SVC)){ - dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); - cortex_a8->curr_mode = ARM_MODE_SVC; + (cortex_a8->curr_mode != ARM_MODE_SVC)) { + dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC); + cortex_a8->curr_mode = ARM_MODE_SVC; LOG_INFO("%x access in kernel space and target not in supervisor", address); return ERROR_OK; } if ((address < os_border) && - (cortex_a8->curr_mode == ARM_MODE_SVC)){ - dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); - cortex_a8->curr_mode = ARM_MODE_ANY; + (cortex_a8->curr_mode == ARM_MODE_SVC)) { + dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); + cortex_a8->curr_mode = ARM_MODE_ANY; } return ERROR_OK; } @@ -141,7 +141,7 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) if (!(cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr |= 0x1U; - retval = armv7a->armv4_5_common.mcr(target, 15, + retval = armv7a->arm.mcr(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); @@ -160,7 +160,7 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) if ( (cortex_a8->cp15_control_reg_curr & 0x1U)) { cortex_a8->cp15_control_reg_curr &= ~0x1U; - retval = armv7a->armv4_5_common.mcr(target, 15, + retval = armv7a->arm.mcr(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ cortex_a8->cp15_control_reg_curr); @@ -175,7 +175,7 @@ static int cortex_a8_mmu_modify(struct target *target, int enable) static int cortex_a8_init_debug_access(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int retval; uint32_t dummy; @@ -223,7 +223,7 @@ static int cortex_a8_exec_opcode(struct target *target, uint32_t dscr; int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; dscr = dscr_p ? *dscr_p : 0; @@ -285,7 +285,7 @@ static int cortex_a8_read_regs_through_mem(struct target *target, uint32_t addre { int retval = ERROR_OK; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; retval = cortex_a8_dap_read_coreregister_u32(target, regfile, 0); if (retval != ERROR_OK) @@ -310,7 +310,7 @@ static int cortex_a8_dap_read_coreregister_u32(struct target *target, uint8_t reg = regnum&0xFF; uint32_t dscr = 0; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; if (reg > 17) return retval; @@ -380,7 +380,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target, uint8_t Rd = regnum&0xFF; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); @@ -464,7 +464,7 @@ static int cortex_a8_dap_write_memap_register_u32(struct target *target, uint32_ { int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; retval = mem_ap_sel_write_atomic_u32(swjdp, swjdp_debugap, address, value); @@ -490,14 +490,14 @@ static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm) static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data) { LOG_DEBUG("write DCC 0x%08" PRIx32, data); - return mem_ap_sel_write_u32(a8->armv7a_common.armv4_5_common.dap, + return mem_ap_sel_write_u32(a8->armv7a_common.arm.dap, swjdp_debugap,a8->armv7a_common.debug_base + CPUDBG_DTRRX, data); } static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, uint32_t *dscr_p) { - struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr = DSCR_INSTR_COMP; int retval; @@ -534,7 +534,7 @@ static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data, static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) { struct cortex_a8_common *a8 = dpm_to_a8(dpm); - struct adiv5_dap *swjdp = a8->armv7a_common.armv4_5_common.dap; + struct adiv5_dap *swjdp = a8->armv7a_common.arm.dap; uint32_t dscr; int retval; @@ -561,7 +561,7 @@ static int cortex_a8_dpm_prepare(struct arm_dpm *dpm) LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); /* Clear DCCRX */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -589,7 +589,7 @@ static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm, return retval; return cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); } @@ -607,7 +607,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -615,7 +615,7 @@ static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm, /* then the opcode, taking data from R0 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); @@ -642,7 +642,7 @@ static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm, /* the opcode, writing data to DCC */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); if (retval != ERROR_OK) @@ -661,7 +661,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, /* the opcode, writing data to R0 */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, opcode, &dscr); if (retval != ERROR_OK) @@ -669,7 +669,7 @@ static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm, /* write R0 to DCC */ retval = cortex_a8_exec_opcode( - a8->armv7a_common.armv4_5_common.target, + a8->armv7a_common.arm.target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0), &dscr); if (retval != ERROR_OK) @@ -743,7 +743,7 @@ static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr) struct arm_dpm *dpm = &a8->armv7a_common.dpm; int retval; - dpm->arm = &a8->armv7a_common.armv4_5_common; + dpm->arm = &a8->armv7a_common.arm; dpm->didr = didr; dpm->prepare = cortex_a8_dpm_prepare; @@ -824,7 +824,7 @@ static int cortex_a8_poll(struct target *target) uint32_t dscr; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; enum target_state prev_target_state = target->state; // toggle to another core is done by gdb as follow // maint packet J core_id @@ -907,7 +907,7 @@ static int cortex_a8_halt(struct target *target) int retval = ERROR_OK; uint32_t dscr; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; /* * Tell the core to be halted by writing DRCR with 0x1 @@ -958,7 +958,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, uint32_t *address, int handle_breakpoints, int debug_execution) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; int retval; uint32_t resume_pc; @@ -987,7 +987,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, #endif /* current = 1: continue on current pc, otherwise continue at
*/ - resume_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + resume_pc = buf_get_u32(arm->pc->value, 0, 32); if (!current) resume_pc = *address; else @@ -996,7 +996,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, /* Make sure that the Armv7 gdb thumb fixups does not * kill the return address */ - switch (armv4_5->core_state) + switch (arm->core_state) { case ARM_STATE_ARM: resume_pc &= 0xFFFFFFFC; @@ -1013,9 +1013,9 @@ static int cortex_a8_internal_restore(struct target *target, int current, return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); - buf_set_u32(armv4_5->pc->value, 0, 32, resume_pc); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, resume_pc); + arm->pc->dirty = 1; + arm->pc->valid = 1; /* restore dpm_mode at system halt */ dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY); /* called it now before restoring context because it uses cpu @@ -1030,7 +1030,7 @@ static int cortex_a8_internal_restore(struct target *target, int current, target->state = TARGET_RUNNING; /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); #if 0 /* the front-end may request us not to handle breakpoints */ @@ -1053,8 +1053,8 @@ static int cortex_a8_internal_restore(struct target *target, int current, static int cortex_a8_internal_restart(struct target *target) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = armv4_5->dap; + struct arm *arm = &armv7a->arm; + struct adiv5_dap *swjdp = arm->dap; int retval; uint32_t dscr; /* @@ -1104,7 +1104,7 @@ static int cortex_a8_internal_restart(struct target *target) target->state = TARGET_RUNNING; /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); return ERROR_OK; } @@ -1179,8 +1179,8 @@ static int cortex_a8_debug_entry(struct target *target) struct working_area *regfile_working_area = NULL; struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct arm *arm = &armv7a->arm; + struct adiv5_dap *swjdp = armv7a->arm.dap; struct reg *reg; LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr); @@ -1248,12 +1248,12 @@ static int cortex_a8_debug_entry(struct target *target) LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr); - arm_set_cpsr(armv4_5, cpsr); + arm_set_cpsr(arm, cpsr); /* update cache */ for (i = 0; i <= ARM_PC; i++) { - reg = arm_reg_current(armv4_5, i); + reg = arm_reg_current(arm, i); buf_set_u32(reg->value, 0, 32, regfile[i]); reg->valid = 1; @@ -1272,7 +1272,7 @@ static int cortex_a8_debug_entry(struct target *target) regfile[ARM_PC] -= 8; } - reg = armv4_5->pc; + reg = arm->pc; buf_set_u32(reg->value, 0, 32, regfile[ARM_PC]); reg->dirty = reg->valid; } @@ -1309,7 +1309,7 @@ static int cortex_a8_post_debug_entry(struct target *target) int retval; /* MRC p15,0,,c1,c0,0 ; Read CP15 System Control Register */ - retval = armv7a->armv4_5_common.mrc(target, 15, + retval = armv7a->arm.mrc(target, 15, 0, 0, /* op1, op2 */ 1, 0, /* CRn, CRm */ &cortex_a8->cp15_control_reg); @@ -1329,8 +1329,8 @@ static int cortex_a8_post_debug_entry(struct target *target) (cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0; armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled = (cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0; - cortex_a8->curr_mode = armv7a->armv4_5_common.core_mode; - + cortex_a8->curr_mode = armv7a->arm.core_mode; + return ERROR_OK; } @@ -1338,7 +1338,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; struct breakpoint *breakpoint = NULL; struct breakpoint stepbreakpoint; struct reg *r; @@ -1351,7 +1351,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, } /* current = 1: continue on current pc, otherwise continue at
*/ - r = armv4_5->pc; + r = arm->pc; if (!current) { buf_set_u32(r->value, 0, 32, address); @@ -1374,7 +1374,7 @@ static int cortex_a8_step(struct target *target, int current, uint32_t address, /* Setup single step breakpoint */ stepbreakpoint.address = address; - stepbreakpoint.length = (armv4_5->core_state == ARM_STATE_THUMB) + stepbreakpoint.length = (arm->core_state == ARM_STATE_THUMB) ? 2 : 4; stepbreakpoint.type = BKPT_HARD; stepbreakpoint.set = 0; @@ -1866,7 +1866,7 @@ static int cortex_a8_assert_reset(struct target *target) } /* registers are now invalid */ - register_cache_invalidate(armv7a->armv4_5_common.core_cache); + register_cache_invalidate(armv7a->arm.core_cache); target->state = TARGET_RESET; @@ -1908,7 +1908,7 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, int retval = ERROR_COMMAND_SYNTAX_ERROR; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; int total_bytes = count * size; int start_byte, nbytes_to_write, i; struct reg *reg; @@ -1923,9 +1923,9 @@ static int cortex_a8_write_apb_ab_memory(struct target *target, return ERROR_TARGET_NOT_HALTED; } - reg = arm_reg_current(armv4_5, 0); + reg = arm_reg_current(arm, 0); reg->dirty = 1; - reg = arm_reg_current(armv4_5, 1); + reg = arm_reg_current(arm, 1); reg->dirty = 1; retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0); @@ -1981,7 +1981,7 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, int retval = ERROR_COMMAND_SYNTAX_ERROR; struct armv7a_common *armv7a = target_to_armv7a(target); - struct arm *armv4_5 = &armv7a->armv4_5_common; + struct arm *arm = &armv7a->arm; int total_bytes = count * size; int start_byte, nbytes_to_read, i; struct reg *reg; @@ -1996,9 +1996,9 @@ static int cortex_a8_read_apb_ab_memory(struct target *target, return ERROR_TARGET_NOT_HALTED; } - reg = arm_reg_current(armv4_5, 0); + reg = arm_reg_current(arm, 0); reg->dirty = 1; - reg = arm_reg_current(armv4_5, 1); + reg = arm_reg_current(arm, 1); reg->dirty = 1; retval = cortex_a8_dap_write_coreregister_u32(target, address & 0xFFFFFFFC, 0); @@ -2046,7 +2046,7 @@ static int cortex_a8_read_phys_memory(struct target *target, uint32_t count, uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; LOG_DEBUG("Reading memory at real address 0x%x; size %d; count %d", @@ -2091,7 +2091,7 @@ static int cortex_a8_read_memory(struct target *target, uint32_t address, uint32_t virt, phys; int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ @@ -2131,7 +2131,7 @@ static int cortex_a8_write_phys_memory(struct target *target, uint32_t count, const uint8_t *buffer) { struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int retval = ERROR_COMMAND_SYNTAX_ERROR; uint8_t apsel = swjdp->apsel; @@ -2173,7 +2173,7 @@ static int cortex_a8_write_phys_memory(struct target *target, /* REVISIT this op is generic ARMv7-A/R stuff */ if (retval == ERROR_OK && target->state == TARGET_HALTED) { - struct arm_dpm *dpm = armv7a->armv4_5_common.dpm; + struct arm_dpm *dpm = armv7a->arm.dpm; retval = dpm->prepare(dpm); if (retval != ERROR_OK) @@ -2237,7 +2237,7 @@ static int cortex_a8_write_memory(struct target *target, uint32_t address, uint32_t virt, phys; int retval; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; /* cortex_a8 handles unaligned memory access */ LOG_DEBUG("Reading memory at address 0x%x; size %d; count %d", address, @@ -2284,7 +2284,7 @@ static int cortex_a8_handle_target_request(void *priv) { struct target *target = priv; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int retval; if (!target_was_examined(target)) @@ -2324,7 +2324,7 @@ static int cortex_a8_examine_first(struct target *target) { struct cortex_a8_common *cortex_a8 = target_to_cortex_a8(target); struct armv7a_common *armv7a = &cortex_a8->armv7a_common; - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; int i; int retval = ERROR_OK; uint32_t didr, ctypr, ttypr, cpuid; @@ -2393,7 +2393,7 @@ static int cortex_a8_examine_first(struct target *target) LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr); LOG_DEBUG("didr = 0x%08" PRIx32, didr); - armv7a->armv4_5_common.core_type = ARM_MODE_MON; + armv7a->arm.core_type = ARM_MODE_MON; retval = cortex_a8_dpm_setup(cortex_a8, didr); if (retval != ERROR_OK) return retval; @@ -2454,14 +2454,14 @@ static int cortex_a8_init_arch_info(struct target *target, struct armv7a_common *armv7a = &cortex_a8->armv7a_common; struct adiv5_dap *dap = &armv7a->dap; - armv7a->armv4_5_common.dap = dap; + armv7a->arm.dap = dap; /* Setup struct cortex_a8_common */ cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC; /* tap has no dap initialized */ if (!tap->dap) { - armv7a->armv4_5_common.dap = dap; + armv7a->arm.dap = dap; /* Setup struct cortex_a8_common */ /* prepare JTAG information for the new target */ @@ -2477,7 +2477,7 @@ static int cortex_a8_init_arch_info(struct target *target, tap->dap = dap; } else - armv7a->armv4_5_common.dap = tap->dap; + armv7a->arm.dap = tap->dap; cortex_a8->fast_reg_read = 0; @@ -2525,7 +2525,7 @@ static int cortex_a8_virt2phys(struct target *target, { int retval = ERROR_FAIL; struct armv7a_common *armv7a = target_to_armv7a(target); - struct adiv5_dap *swjdp = armv7a->armv4_5_common.dap; + struct adiv5_dap *swjdp = armv7a->arm.dap; uint8_t apsel = swjdp->apsel; if (apsel == swjdp_memoryap) { diff --git a/src/target/cortex_a.h b/src/target/cortex_a.h index 17e44e210..e736857a1 100644 --- a/src/target/cortex_a.h +++ b/src/target/cortex_a.h @@ -85,7 +85,7 @@ static inline struct cortex_a8_common * target_to_cortex_a8(struct target *target) { return container_of(target->arch_info, struct cortex_a8_common, - armv7a_common.armv4_5_common); + armv7a_common.arm); } #endif /* CORTEX_A8_H */ diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 9bd45bedf..3617b2be7 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -61,8 +61,8 @@ static int feroceon_assert_reset(struct target *target) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; int ud = arm7_9->use_dbgrq; arm7_9->use_dbgrq = 0; @@ -115,8 +115,8 @@ static int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) static void feroceon_change_to_arm(struct target *target, uint32_t *r0, uint32_t *pc) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; /* @@ -163,8 +163,8 @@ static void feroceon_read_core_regs(struct target *target, uint32_t mask, uint32_t* core_regs[16]) { int i; - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); @@ -183,8 +183,8 @@ static void feroceon_read_core_regs_target_buffer(struct target *target, uint32_t mask, void* buffer, int size) { int i; - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; uint32_t *buf_u32 = buffer; @@ -219,8 +219,8 @@ static void feroceon_read_core_regs_target_buffer(struct target *target, static void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_MRS(0, spsr & 1), 0, NULL, 0); @@ -242,8 +242,8 @@ static void feroceon_read_xpsr(struct target *target, uint32_t *xpsr, int spsr) static void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr); @@ -284,8 +284,8 @@ static void feroceon_write_xpsr(struct target *target, uint32_t xpsr, int spsr) static void feroceon_write_xpsr_im8(struct target *target, uint8_t xpsr_im, int rot, int spsr) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr); @@ -303,8 +303,8 @@ static void feroceon_write_core_regs(struct target *target, uint32_t mask, uint32_t core_regs[16]) { int i; - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, mask & 0xffff, 0, 0), 0, NULL, 0); @@ -322,8 +322,8 @@ static void feroceon_write_core_regs(struct target *target, static void feroceon_branch_resume(struct target *target) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -339,11 +339,11 @@ static void feroceon_branch_resume_thumb(struct target *target) { LOG_DEBUG("-"); - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; - uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); - uint32_t pc = buf_get_u32(armv4_5->pc->value, 0, 32); + uint32_t r0 = buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); + uint32_t pc = buf_get_u32(arm->pc->value, 0, 32); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0); @@ -373,8 +373,8 @@ static void feroceon_branch_resume_thumb(struct target *target) static int feroceon_read_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int err; @@ -396,8 +396,8 @@ static int feroceon_read_cp15(struct target *target, uint32_t op1, static int feroceon_write_cp15(struct target *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; arm9tdmi_clock_out(jtag_info, ARMV4_5_LDMIA(0, 1, 0, 0), 0, NULL, 0); @@ -415,8 +415,8 @@ static int feroceon_write_cp15(struct target *target, uint32_t op1, static void feroceon_set_dbgrq(struct target *target) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; buf_set_u32(dbg_ctrl->value, 0, 8, 2); @@ -425,8 +425,8 @@ static void feroceon_set_dbgrq(struct target *target) static void feroceon_enable_single_step(struct target *target, uint32_t next_pc) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; /* set a breakpoint there */ embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], next_pc); @@ -438,8 +438,8 @@ static void feroceon_enable_single_step(struct target *target, uint32_t next_pc) static void feroceon_disable_single_step(struct target *target) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]); embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]); @@ -463,9 +463,9 @@ static int feroceon_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer) { int retval; - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; - enum arm_state core_state = armv4_5->core_state; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; + enum arm_state core_state = arm->core_state; uint32_t x, flip, shift, save[7]; uint32_t i; @@ -527,14 +527,14 @@ static int feroceon_bulk_write_memory(struct target *target, /* backup clobbered processor state */ for (i = 0; i <= 5; i++) - save[i] = buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32); - save[i] = buf_get_u32(armv4_5->pc->value, 0, 32); + save[i] = buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32); + save[i] = buf_get_u32(arm->pc->value, 0, 32); /* set up target address in r0 */ - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, address); - armv4_5->core_cache->reg_list[0].valid = 1; - armv4_5->core_cache->reg_list[0].dirty = 1; - armv4_5->core_state = ARM_STATE_ARM; + buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, address); + arm->core_cache->reg_list[0].valid = 1; + arm->core_cache->reg_list[0].dirty = 1; + arm->core_state = ARM_STATE_ARM; embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0); arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1); @@ -564,7 +564,7 @@ static int feroceon_bulk_write_memory(struct target *target, retval = target_wait_state(target, TARGET_HALTED, 500); if (retval == ERROR_OK) { uint32_t endaddress = - buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); + buf_get_u32(arm->core_cache->reg_list[0].value, 0, 32); if (endaddress != address + count*4) { LOG_ERROR("DCC write failed," " expected end address 0x%08" PRIx32 @@ -577,14 +577,14 @@ static int feroceon_bulk_write_memory(struct target *target, /* restore target state */ for (i = 0; i <= 5; i++) { - buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, save[i]); - armv4_5->core_cache->reg_list[i].valid = 1; - armv4_5->core_cache->reg_list[i].dirty = 1; + buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, save[i]); + arm->core_cache->reg_list[i].valid = 1; + arm->core_cache->reg_list[i].dirty = 1; } - buf_set_u32(armv4_5->pc->value, 0, 32, save[i]); - armv4_5->pc->valid = 1; - armv4_5->pc->dirty = 1; - armv4_5->core_state = core_state; + buf_set_u32(arm->pc->value, 0, 32, save[i]); + arm->pc->valid = 1; + arm->pc->dirty = 1; + arm->core_state = core_state; return retval; } @@ -598,8 +598,8 @@ static int feroceon_init_target(struct command_context *cmd_ctx, static void feroceon_common_setup(struct target *target) { - struct arm *armv4_5 = target->arch_info; - struct arm7_9_common *arm7_9 = armv4_5->arch_info; + struct arm *arm = target->arch_info; + struct arm7_9_common *arm7_9 = arm->arch_info; /* override some insn sequence functions */ arm7_9->change_to_arm = feroceon_change_to_arm; @@ -655,7 +655,7 @@ static int dragonite_target_create(struct target *target, Jim_Interp *interp) static int feroceon_examine(struct target *target) { - struct arm *armv4_5; + struct arm *arm; struct arm7_9_common *arm7_9; int retval; @@ -663,8 +663,8 @@ static int feroceon_examine(struct target *target) if (retval != ERROR_OK) return retval; - armv4_5 = target->arch_info; - arm7_9 = armv4_5->arch_info; + arm = target->arch_info; + arm7_9 = arm->arch_info; /* the COMMS_CTRL bits are all contiguous */ if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6) diff --git a/src/target/xscale.c b/src/target/xscale.c index 5ea507192..6f00aea7e 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -825,7 +825,7 @@ static int xscale_update_vectors(struct target *target) static int xscale_arch_state(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct arm *armv4_5 = &xscale->armv4_5_common; + struct arm *arm = &xscale->arm; static const char *state[] = { @@ -837,7 +837,7 @@ static int xscale_arch_state(struct target *target) "", "\n(processor reset)", "\n(trace buffer full)" }; - if (armv4_5->common_magic != ARM_COMMON_MAGIC) + if (arm->common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("BUG: called for a non-ARMv4/5 target"); return ERROR_COMMAND_SYNTAX_ERROR; @@ -896,7 +896,7 @@ static int xscale_poll(struct target *target) static int xscale_debug_entry(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct arm *armv4_5 = &xscale->armv4_5_common; + struct arm *arm = &xscale->arm; uint32_t pc; uint32_t buffer[10]; unsigned i; @@ -913,44 +913,44 @@ static int xscale_debug_entry(struct target *target) return retval; /* move r0 from buffer to register cache */ - buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]); - armv4_5->core_cache->reg_list[0].dirty = 1; - armv4_5->core_cache->reg_list[0].valid = 1; + buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]); + arm->core_cache->reg_list[0].dirty = 1; + arm->core_cache->reg_list[0].valid = 1; LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]); /* move pc from buffer to register cache */ - buf_set_u32(armv4_5->pc->value, 0, 32, buffer[1]); - armv4_5->pc->dirty = 1; - armv4_5->pc->valid = 1; + buf_set_u32(arm->pc->value, 0, 32, buffer[1]); + arm->pc->dirty = 1; + arm->pc->valid = 1; LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]); /* move data from buffer to register cache */ for (i = 1; i <= 7; i++) { - buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); - armv4_5->core_cache->reg_list[i].dirty = 1; - armv4_5->core_cache->reg_list[i].valid = 1; + buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]); + arm->core_cache->reg_list[i].dirty = 1; + arm->core_cache->reg_list[i].valid = 1; LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]); } - arm_set_cpsr(armv4_5, buffer[9]); + arm_set_cpsr(arm, buffer[9]); LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]); - if (!is_arm_mode(armv4_5->core_mode)) + if (!is_arm_mode(arm->core_mode)) { target->state = TARGET_UNKNOWN; LOG_ERROR("cpsr contains invalid mode value - communication failure"); return ERROR_TARGET_FAILURE; } LOG_DEBUG("target entered debug state in %s mode", - arm_mode_name(armv4_5->core_mode)); + arm_mode_name(arm->core_mode)); /* get banked registers, r8 to r14, and spsr if not in USR/SYS mode */ - if (armv4_5->spsr) { + if (arm->spsr) { xscale_receive(target, buffer, 8); - buf_set_u32(armv4_5->spsr->value, 0, 32, buffer[7]); - armv4_5->spsr->dirty = false; - armv4_5->spsr->valid = true; + buf_set_u32(arm->spsr->value, 0, 32, buffer[7]); + arm->spsr->dirty = false; + arm->spsr->valid = true; } else { @@ -961,7 +961,7 @@ static int xscale_debug_entry(struct target *target) /* move data from buffer to right banked register in cache */ for (i = 8; i <= 14; i++) { - struct reg *r = arm_reg_current(armv4_5, i); + struct reg *r = arm_reg_current(arm, i); buf_set_u32(r->value, 0, 32, buffer[i - 8]); r->dirty = false; @@ -978,7 +978,7 @@ static int xscale_debug_entry(struct target *target) moe = buf_get_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 2, 3); /* stored PC (for calculating fixup) */ - pc = buf_get_u32(armv4_5->pc->value, 0, 32); + pc = buf_get_u32(arm->pc->value, 0, 32); switch (moe) { @@ -1025,7 +1025,7 @@ static int xscale_debug_entry(struct target *target) } /* apply PC fixup */ - buf_set_u32(armv4_5->pc->value, 0, 32, pc); + buf_set_u32(arm->pc->value, 0, 32, pc); /* on the first debug entry, identify cache type */ if (xscale->armv4_5_mmu.armv4_5_cache.ctype == -1) @@ -1183,7 +1183,7 @@ static int xscale_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution) { struct xscale_common *xscale = target_to_xscale(target); - struct arm *armv4_5 = &xscale->armv4_5_common; + struct arm *arm = &xscale->arm; uint32_t current_pc; int retval; int i; @@ -1207,15 +1207,15 @@ static int xscale_resume(struct target *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->pc->value, 0, 32, address); + buf_set_u32(arm->pc->value, 0, 32, address); - current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); /* if we're at the reset vector, we have to simulate the branch */ if (current_pc == 0x0) { arm_simulate_step(target, NULL); - current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); } /* the front-end may request us not to handle breakpoints */ @@ -1223,7 +1223,7 @@ static int xscale_resume(struct target *target, int current, { struct breakpoint *breakpoint; breakpoint = breakpoint_find(target, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); if (breakpoint != NULL) { uint32_t next_pc; @@ -1254,22 +1254,23 @@ static int xscale_resume(struct target *target, int current, /* send CPSR */ xscale_send_u32(target, - buf_get_u32(armv4_5->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", + i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ xscale_send_u32(target, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); LOG_DEBUG("writing PC with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); /* disable trace data collection in xscale_debug_entry() */ saved_trace_mode = xscale->trace.mode; @@ -1322,28 +1323,29 @@ static int xscale_resume(struct target *target, int current, xscale_send_u32(target, 0x30); /* send CPSR */ - xscale_send_u32(target, buf_get_u32(armv4_5->cpsr->value, 0, 32)); + xscale_send_u32(target, buf_get_u32(arm->cpsr->value, 0, 32)); LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); for (i = 7; i >= 0; i--) { /* send register */ - xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); - LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", + i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ - xscale_send_u32(target, buf_get_u32(armv4_5->pc->value, 0, 32)); + xscale_send_u32(target, buf_get_u32(arm->pc->value, 0, 32)); LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); target->debug_reason = DBG_REASON_NOTHALTED; if (!debug_execution) { /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); target->state = TARGET_RUNNING; target_call_event_callbacks(target, TARGET_EVENT_RESUMED); } @@ -1362,7 +1364,7 @@ static int xscale_step_inner(struct target *target, int current, uint32_t address, int handle_breakpoints) { struct xscale_common *xscale = target_to_xscale(target); - struct arm *armv4_5 = &xscale->armv4_5_common; + struct arm *arm = &xscale->arm; uint32_t next_pc; int retval; int i; @@ -1373,7 +1375,7 @@ static int xscale_step_inner(struct target *target, int current, if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK) { uint32_t current_opcode, current_pc; - current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); target_read_u32(target, current_pc, ¤t_opcode); LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode); @@ -1403,32 +1405,34 @@ static int xscale_step_inner(struct target *target, int current, /* send CPSR */ retval = xscale_send_u32(target, - buf_get_u32(armv4_5->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); if (retval != ERROR_OK) return retval; LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->cpsr->value, 0, 32)); + buf_get_u32(arm->cpsr->value, 0, 32)); - for (i = 7; i >= 0; i--) - { + for (i = 7; i >= 0; i--) { /* send register */ - if ((retval = xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32))) != ERROR_OK) + retval = xscale_send_u32(target, + buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); + if (retval != ERROR_OK) return retval; - LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32)); + LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i, + buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32)); } /* send PC */ retval = xscale_send_u32(target, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); if (retval != ERROR_OK) return retval; LOG_DEBUG("wrote PC with value 0x%8.8" PRIx32, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); target_call_event_callbacks(target, TARGET_EVENT_RESUMED); /* registers are now invalid */ - register_cache_invalidate(armv4_5->core_cache); + register_cache_invalidate(arm->core_cache); /* wait for and process debug entry */ if ((retval = xscale_debug_entry(target)) != ERROR_OK) @@ -1446,7 +1450,7 @@ static int xscale_step_inner(struct target *target, int current, static int xscale_step(struct target *target, int current, uint32_t address, int handle_breakpoints) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); struct breakpoint *breakpoint = NULL; uint32_t current_pc; @@ -1460,16 +1464,16 @@ static int xscale_step(struct target *target, int current, /* current = 1: continue on current pc, otherwise continue at
*/ if (!current) - buf_set_u32(armv4_5->pc->value, 0, 32, address); + buf_set_u32(arm->pc->value, 0, 32, address); - current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); /* if we're at the reset vector, we have to simulate the step */ if (current_pc == 0x0) { if ((retval = arm_simulate_step(target, NULL)) != ERROR_OK) return retval; - current_pc = buf_get_u32(armv4_5->pc->value, 0, 32); + current_pc = buf_get_u32(arm->pc->value, 0, 32); LOG_DEBUG("current pc %" PRIx32, current_pc); target->debug_reason = DBG_REASON_SINGLESTEP; @@ -1481,7 +1485,7 @@ static int xscale_step(struct target *target, int current, /* the front-end may request us not to handle breakpoints */ if (handle_breakpoints) breakpoint = breakpoint_find(target, - buf_get_u32(armv4_5->pc->value, 0, 32)); + buf_get_u32(arm->pc->value, 0, 32)); if (breakpoint != NULL) { retval = xscale_unset_breakpoint(target, breakpoint); if (retval != ERROR_OK) @@ -1573,7 +1577,7 @@ static int xscale_deassert_reset(struct target *target) xscale->trace.mode = XSCALE_TRACE_DISABLED; xscale_free_trace_data(xscale); - register_cache_invalidate(xscale->armv4_5_common.core_cache); + register_cache_invalidate(xscale->arm.core_cache); /* FIXME mark hardware watchpoints got unset too. Also, * at least some of the XScale registers are invalid... @@ -1700,7 +1704,7 @@ static int xscale_write_core_reg(struct target *target, struct reg *r, static int xscale_full_context(struct target *target) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); uint32_t *buffer; @@ -1733,7 +1737,7 @@ static int xscale_full_context(struct target *target) */ for (j = 0; valid && j <= 16; j++) { - if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + if (!ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, j).valid) valid = false; } @@ -1751,7 +1755,7 @@ static int xscale_full_context(struct target *target) */ if (mode != ARM_MODE_SYS) { /* SPSR */ - r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + r = &ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, 16); xscale_receive(target, buffer, 8); @@ -1766,7 +1770,7 @@ static int xscale_full_context(struct target *target) /* move data from buffer to register cache */ for (j = 8; j <= 14; j++) { - r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + r = &ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, j); buf_set_u32(r->value, 0, 32, buffer[j - 8]); @@ -1782,7 +1786,7 @@ static int xscale_full_context(struct target *target) static int xscale_restore_banked(struct target *target) { - struct arm *armv4_5 = target_to_arm(target); + struct arm *arm = target_to_arm(target); int i, j; @@ -1808,7 +1812,7 @@ static int xscale_restore_banked(struct target *target) /* check if there are dirty registers in this mode */ for (j = 8; j <= 14; j++) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, j).dirty) goto dirty; } @@ -1816,7 +1820,7 @@ static int xscale_restore_banked(struct target *target) /* if not USR/SYS, check if the SPSR needs to be written */ if (mode != ARM_MODE_SYS) { - if (ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + if (ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, 16).dirty) goto dirty; } @@ -1835,7 +1839,7 @@ dirty: * but this protocol doesn't understand that nuance. */ for (j = 8; j <= 14; j++) { - r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + r = &ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, j); xscale_send_u32(target, buf_get_u32(r->value, 0, 32)); r->dirty = false; @@ -1843,7 +1847,7 @@ dirty: /* send spsr if not in USR/SYS mode */ if (mode != ARM_MODE_SYS) { - r = &ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, + r = &ARMV4_5_CORE_REG_MODE(arm->core_cache, mode, 16); xscale_send_u32(target, buf_get_u32(r->value, 0, 32)); r->dirty = false; @@ -2629,7 +2633,7 @@ static int xscale_write_dcsr_sw(struct target *target, uint32_t value) static int xscale_read_trace(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct arm *armv4_5 = &xscale->armv4_5_common; + struct arm *arm = &xscale->arm; struct xscale_trace_data **trace_data_p; /* 258 words from debug handler @@ -2710,7 +2714,7 @@ static int xscale_read_trace(struct target *target) (*trace_data_p)->chkpt0 = trace_buffer[256]; (*trace_data_p)->chkpt1 = trace_buffer[257]; (*trace_data_p)->last_instruction = - buf_get_u32(armv4_5->pc->value, 0, 32); + buf_get_u32(arm->pc->value, 0, 32); (*trace_data_p)->entries = malloc(sizeof(struct xscale_trace_entry) * (256 - j)); (*trace_data_p)->depth = 256 - j; (*trace_data_p)->num_checkpoints = num_checkpoints; @@ -3030,13 +3034,13 @@ static const struct reg_arch_type xscale_reg_type = { static void xscale_build_reg_cache(struct target *target) { struct xscale_common *xscale = target_to_xscale(target); - struct arm *armv4_5 = &xscale->armv4_5_common; + struct arm *arm = &xscale->arm; struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache); struct xscale_reg *arch_info = malloc(sizeof(xscale_reg_arch_info)); int i; int num_regs = ARRAY_SIZE(xscale_reg_arch_info); - (*cache_p) = arm_build_reg_cache(target, armv4_5); + (*cache_p) = arm_build_reg_cache(target, arm); (*cache_p)->next = malloc(sizeof(struct reg_cache)); cache_p = &(*cache_p)->next; @@ -3073,11 +3077,11 @@ static int xscale_init_target(struct command_context *cmd_ctx, static int xscale_init_arch_info(struct target *target, struct xscale_common *xscale, struct jtag_tap *tap, const char *variant) { - struct arm *armv4_5; + struct arm *arm; uint32_t high_reset_branch, low_reset_branch; int i; - armv4_5 = &xscale->armv4_5_common; + arm = &xscale->arm; /* store architecture specfic data */ xscale->common_magic = XSCALE_COMMON_MAGIC; @@ -3167,12 +3171,12 @@ static int xscale_init_arch_info(struct target *target, xscale->trace.fill_counter = 0; /* prepare ARMv4/5 specific information */ - armv4_5->arch_info = xscale; - armv4_5->read_core_reg = xscale_read_core_reg; - armv4_5->write_core_reg = xscale_write_core_reg; - armv4_5->full_context = xscale_full_context; + arm->arch_info = xscale; + arm->read_core_reg = xscale_read_core_reg; + arm->write_core_reg = xscale_write_core_reg; + arm->full_context = xscale_full_context; - arm_init_arch_info(target, armv4_5); + arm_init_arch_info(target, arm); xscale->armv4_5_mmu.armv4_5_cache.ctype = -1; xscale->armv4_5_mmu.get_ttb = xscale_get_ttb; diff --git a/src/target/xscale.h b/src/target/xscale.h index e480da930..49d4c71ec 100644 --- a/src/target/xscale.h +++ b/src/target/xscale.h @@ -91,7 +91,7 @@ struct xscale_trace struct xscale_common { /* armv4/5 common stuff */ - struct arm armv4_5_common; + struct arm arm; int common_magic; @@ -148,7 +148,7 @@ static inline struct xscale_common * target_to_xscale(struct target *target) { return container_of(target->arch_info, struct xscale_common, - armv4_5_common); + arm); } struct xscale_reg