nds32: support FreeRTOS
Change-Id: I117b5541fb19388c0f5c2344ee42d9151c9a222e Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1577 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>__archive__
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a8d0fec087
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356f8a7412
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@ -72,7 +72,19 @@ const struct FreeRTOS_params FreeRTOS_params_list[] = {
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0, /* thread_stack_offset; */
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52, /* thread_name_offset; */
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&rtos_standard_Cortex_M3_stacking, /* stacking_info */
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}
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},
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{
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"nds32_v3", /* target_name */
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4, /* thread_count_width; */
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4, /* pointer_width; */
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16, /* list_next_offset; */
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20, /* list_width; */
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8, /* list_elem_next_offset; */
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12, /* list_elem_content_offset */
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0, /* thread_stack_offset; */
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52, /* thread_name_offset; */
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&rtos_standard_NDS32_N1068_stacking, /* stacking_info */
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},
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};
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#define FREERTOS_NUM_PARAMS ((int)(sizeof(FreeRTOS_params_list)/sizeof(struct FreeRTOS_params)))
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@ -83,6 +83,45 @@ static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[
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{ 0x04, 32 }, /* CSPR */
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};
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static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offsets[] = {
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{ 0x88, 32 }, /* R0 */
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{ 0x8C, 32 }, /* R1 */
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{ 0x14, 32 }, /* R2 */
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{ 0x18, 32 }, /* R3 */
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{ 0x1C, 32 }, /* R4 */
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{ 0x20, 32 }, /* R5 */
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{ 0x24, 32 }, /* R6 */
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{ 0x28, 32 }, /* R7 */
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{ 0x2C, 32 }, /* R8 */
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{ 0x30, 32 }, /* R9 */
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{ 0x34, 32 }, /* R10 */
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{ 0x38, 32 }, /* R11 */
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{ 0x3C, 32 }, /* R12 */
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{ 0x40, 32 }, /* R13 */
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{ 0x44, 32 }, /* R14 */
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{ 0x48, 32 }, /* R15 */
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{ 0x4C, 32 }, /* R16 */
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{ 0x50, 32 }, /* R17 */
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{ 0x54, 32 }, /* R18 */
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{ 0x58, 32 }, /* R19 */
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{ 0x5C, 32 }, /* R20 */
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{ 0x60, 32 }, /* R21 */
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{ 0x64, 32 }, /* R22 */
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{ 0x68, 32 }, /* R23 */
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{ 0x6C, 32 }, /* R24 */
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{ 0x70, 32 }, /* R25 */
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{ 0x74, 32 }, /* R26 */
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{ 0x78, 32 }, /* R27 */
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{ 0x7C, 32 }, /* R28 */
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{ 0x80, 32 }, /* R29 */
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{ 0x84, 32 }, /* R30 (LP) */
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{ 0x00, 32 }, /* R31 (SP) */
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{ 0x04, 32 }, /* PSW */
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{ 0x08, 32 }, /* IPC */
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{ 0x0C, 32 }, /* IPSW */
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{ 0x10, 32 }, /* IFC_LP */
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};
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const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
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0x40, /* stack_registers_size */
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-1, /* stack_growth_direction */
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@ -99,3 +138,11 @@ const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
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8, /* stack_alignment */
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rtos_standard_Cortex_R4_stack_offsets /* register_offsets */
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};
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const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking = {
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0x90, /* stack_registers_size */
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-1, /* stack_growth_direction */
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32, /* num_output_registers */
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8, /* stack_alignment */
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rtos_standard_NDS32_N1068_stack_offsets /* register_offsets */
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};
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@ -29,5 +29,6 @@
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extern const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking;
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extern const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking;
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extern const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking;
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#endif /* ifndef INCLUDED_RTOS_STANDARD_STACKINGS_H_ */
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