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- added patch to solve problem with AT91SAM7SE MCU have 3, rather than just 2 GPNVM bits. 

(Thanks to Pavel for the patch)

git-svn-id: svn://svn.berlios.de/openocd/trunk@317 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
mifi 2008-02-22 16:13:07 +00:00
parent 2ab0530301
commit 34bc9457e9
1 changed files with 3 additions and 3 deletions
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6
src/flash/at91sam7.c
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@ -467,8 +467,8 @@ int at91sam7_read_part_info(struct flash_bank_s *bank)
if (at91sam7_info->cidr_arch == 0x72 ) if (at91sam7_info->cidr_arch == 0x72 )
{ {
at91sam7_info->num_nvmbits = 2; at91sam7_info->num_nvmbits = 3;
at91sam7_info->nvmbits = (status>>8)&0x03; at91sam7_info->nvmbits = (status>>8)&0x07;
bank->base = 0x100000; bank->base = 0x100000;
bank->bus_width = 4; bank->bus_width = 4;
if (bank->size==0x80000) /* AT91SAM7SE512 */ if (bank->size==0x80000) /* AT91SAM7SE512 */
@ -892,7 +892,7 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
} }
/* /*
* On AT91SAM7S: When the gpnmv bits are set with * On AT91SAM7S: When the gpnvm bits are set with
* > at91sam7 gpnvm 0 bitnr set * > at91sam7 gpnvm 0 bitnr set
* the changes are not visible in the flash controller status register MC_FSR * the changes are not visible in the flash controller status register MC_FSR
* until the processor has been reset. * until the processor has been reset.