From 34b32d613af913645bdb0b0e79f10bf0f302ff33 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 26 Feb 2016 21:54:22 +0100 Subject: [PATCH] arm_disassembler: bugfix, MRRC instruction not recognized A copy-and-paste error in the arm_disassembler opcode evaluation disabled the recognition of MRRC instructions. According to the arm architecture ref. manual issue E or later, MRRC and MCRR instructions are identified by opcode bits 20-27: MCRR = 0xc4, MRRC = 0xc5. Error found by static code analysis using a semantic pattern to detect duplicated tests xand.cocci, see coccinellery.org Change-Id: Ic41426edb51c6816e11dc3d35ef9382ab34af486 Signed-off-by: Alexander Kurz Reviewed-on: http://openocd.zylin.com/3363 Reviewed-by: Uwe Bonnes Tested-by: jenkins Reviewed-by: Andreas Fritiofson --- src/target/arm_disassembler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 65086c2fd..5cec6d67a 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -278,7 +278,7 @@ static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint8_t cp_num = (opcode & 0xf00) >> 8; /* MCRR or MRRC */ - if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c400000)) { + if (((opcode & 0x0ff00000) == 0x0c400000) || ((opcode & 0x0ff00000) == 0x0c500000)) { uint8_t cp_opcode, Rd, Rn, CRm; char *mnemonic;