ETM: rename registers, doc tweaks
The register names are perversely not documented as zero-indexed, so rename them to match that convention. Also switch to lowercase suffixes and infix numbering, matching ETB and EmbeddedICE usage. Update docs to be a bit more accurate, especially regarding what the "trigger" event can cause; and to split the issues into a few more paragraphs, for clarity. Make "configure" helptext point out that "oocd_trace" is prototype hardware, not anything "real". Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
3537c368fe
commit
344bed2f7e
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@ -377,7 +377,8 @@ AC_ARG_ENABLE(usbprog,
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[build_usbprog=$enableval], [build_usbprog=no])
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AC_ARG_ENABLE(oocd_trace,
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AS_HELP_STRING([--enable-oocd_trace], [Enable building support for the OpenOCD+trace ETM capture device]),
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AS_HELP_STRING([--enable-oocd_trace],
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[Enable building support for some prototype OpenOCD+trace ETM capture hardware]),
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[build_oocd_trace=$enableval], [build_oocd_trace=no])
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AC_ARG_ENABLE(jlink,
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@ -5114,14 +5114,23 @@ ETM support in OpenOCD doesn't seem to be widely used yet.
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@quotation Issues
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ETM support may be buggy, and at least some @command{etm config}
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parameters should be detected by asking the ETM for them.
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ETM trigger events could also implement a kind of complex
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hardware breakpoint, much more powerful than the simple
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watchpoint hardware exported by EmbeddedICE modules.
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@emph{Such breakpoints can be triggered even when using the
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dummy trace port driver}.
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It seems like a GDB hookup should be possible,
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as well as triggering trace on specific events
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as well as tracing only during specific states
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(perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
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There should be GUI tools to manipulate saved trace data and help
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analyse it in conjunction with the source code.
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It's unclear how much of a common interface is shared
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with the current XScale trace support, or should be
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shared with eventual Nexus-style trace module support.
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At this writing (September 2009) only ARM7 and ARM9 support
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for ETM modules is available. The code should be able to
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work with some newer cores; but not all of them support
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@ -5135,7 +5144,10 @@ ETM setup is coupled with the trace port driver configuration.
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Declares the ETM associated with @var{target}, and associates it
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with a given trace port @var{driver}. @xref{Trace Port Drivers}.
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Several of the parameters must reflect the trace port configuration.
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Several of the parameters must reflect the trace port capabilities,
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which are a function of silicon capabilties (exposed later
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using @command{etm info}) and of what hardware is connected to
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that port (such as an external pod, or ETB).
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The @var{width} must be either 4, 8, or 16.
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The @var{mode} must be @option{normal}, @option{multiplexted},
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or @option{demultiplexted}.
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@ -5151,6 +5163,9 @@ what CPU activities are traced.
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@deffn Command {etm info}
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Displays information about the current target's ETM.
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This includes resource counts from the @code{ETM_CONFIG} register,
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as well as silicon capabilities (except on rather old modules).
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from the @code{ETM_SYS_CONFIG} register.
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@end deffn
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@deffn Command {etm status}
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101
src/target/etm.c
101
src/target/etm.c
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@ -76,47 +76,46 @@ struct etm_reg_info {
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/* basic registers that are always there given the right ETM version */
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static const struct etm_reg_info etm_core[] = {
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/* NOTE: we "know" ETM_CONFIG is listed first */
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{ ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
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{ ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
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/* ETM Trace Registers */
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{ ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
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{ ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
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{ ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_ASIC_CTRL", },
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{ ETM_STATUS, 3, RO, 0x11, "ETM_STATUS", },
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{ ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_SYS_CONFIG", },
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{ ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
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{ ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
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{ ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
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{ ETM_STATUS, 3, RO, 0x11, "ETM_status", },
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{ ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
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/* TraceEnable configuration */
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{ ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
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{ ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_TRACE_EN_CTRL2", },
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{ ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
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{ ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
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{ ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
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{ ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
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{ ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
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{ ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
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/* ViewData configuration (data trace) */
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{ ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
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{ ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
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{ ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
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{ ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
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{ ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
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{ ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
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{ ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
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{ ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
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/* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
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{ 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
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{ 0x79, 32, RO, 0x20, "ETM_ID", },
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{ 0x78, 12, WO, 0x20, "ETM_sync_freq", },
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{ 0x79, 32, RO, 0x20, "ETM_id", },
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};
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static const struct etm_reg_info etm_fifofull[] = {
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/* FIFOFULL configuration */
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{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
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{ ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
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{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
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{ ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
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};
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static const struct etm_reg_info etm_addr_comp[] = {
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/* Address comparator register pairs */
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#define ADDR_COMPARATOR(i) \
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{ ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
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"ETM_ADDR_COMPARATOR_VALUE" #i, }, \
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{ ETM_ADDR_ACCESS_TYPE + (i), 7, WO, 0x10, \
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"ETM_ADDR_ACCESS_TYPE" #i, }
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ADDR_COMPARATOR(0),
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{ ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
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"ETM_addr_" #i "_comparator_value", }, \
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{ ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
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"ETM_addr_" #i "_access_type", }
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ADDR_COMPARATOR(1),
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ADDR_COMPARATOR(2),
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ADDR_COMPARATOR(3),
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@ -124,8 +123,8 @@ static const struct etm_reg_info etm_addr_comp[] = {
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ADDR_COMPARATOR(5),
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ADDR_COMPARATOR(6),
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ADDR_COMPARATOR(7),
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ADDR_COMPARATOR(8),
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ADDR_COMPARATOR(9),
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ADDR_COMPARATOR(10),
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ADDR_COMPARATOR(11),
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@ -133,17 +132,17 @@ static const struct etm_reg_info etm_addr_comp[] = {
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ADDR_COMPARATOR(13),
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ADDR_COMPARATOR(14),
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ADDR_COMPARATOR(15),
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ADDR_COMPARATOR(16),
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#undef ADDR_COMPARATOR
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};
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static const struct etm_reg_info etm_data_comp[] = {
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/* Data Value Comparators (NOTE: odd addresses are reserved) */
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#define DATA_COMPARATOR(i) \
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{ ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
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"ETM_DATA_COMPARATOR_VALUE" #i, }, \
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{ ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
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"ETM_DATA_COMPARATOR_MASK" #i, }
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DATA_COMPARATOR(0),
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{ ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
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"ETM_data_" #i "_comparator_value", }, \
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{ ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
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"ETM_data_" #i "_comparator_mask", }
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DATA_COMPARATOR(1),
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DATA_COMPARATOR(2),
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DATA_COMPARATOR(3),
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@ -151,30 +150,31 @@ static const struct etm_reg_info etm_data_comp[] = {
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DATA_COMPARATOR(5),
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DATA_COMPARATOR(6),
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DATA_COMPARATOR(7),
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DATA_COMPARATOR(8),
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#undef DATA_COMPARATOR
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};
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static const struct etm_reg_info etm_counters[] = {
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#define ETM_COUNTER(i) \
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{ ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
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"ETM_COUNTER_RELOAD_VALUE" #i, }, \
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{ ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
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"ETM_COUNTER_ENABLE" #i, }, \
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{ ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
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"ETM_COUNTER_RELOAD_EVENT" #i, }, \
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{ ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
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"ETM_COUNTER_VALUE" #i, }
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ETM_COUNTER(0),
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{ ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
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"ETM_counter_" #i "_reload_value", }, \
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{ ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
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"ETM_counter_" #i "_enable", }, \
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{ ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
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"ETM_counter_" #i "_reload_event", }, \
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{ ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
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"ETM_counter_" #i "_value", }
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ETM_COUNTER(1),
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ETM_COUNTER(2),
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ETM_COUNTER(3),
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ETM_COUNTER(4),
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#undef ETM_COUNTER
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};
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static const struct etm_reg_info etm_sequencer[] = {
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#define ETM_SEQ(i) \
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{ ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
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"ETM_SEQUENCER_EVENT" #i, }
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"ETM_sequencer_event" #i, }
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ETM_SEQ(0), /* 1->2 */
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ETM_SEQ(1), /* 2->1 */
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ETM_SEQ(2), /* 2->3 */
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@ -183,18 +183,18 @@ static const struct etm_reg_info etm_sequencer[] = {
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ETM_SEQ(5), /* 1->3 */
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#undef ETM_SEQ
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/* 0x66 reserved */
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{ ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_SEQUENCER_STATE", },
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{ ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
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};
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static const struct etm_reg_info etm_outputs[] = {
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#define ETM_OUTPUT(i) \
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{ ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
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"ETM_EXTERNAL_OUTPUT" #i, }
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{ ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
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"ETM_external_output" #i, }
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ETM_OUTPUT(0),
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ETM_OUTPUT(1),
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ETM_OUTPUT(2),
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ETM_OUTPUT(3),
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ETM_OUTPUT(4),
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#undef ETM_OUTPUT
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};
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@ -202,10 +202,10 @@ static const struct etm_reg_info etm_outputs[] = {
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/* registers from 0x6c..0x7f were added after ETMv1.3 */
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/* Context ID Comparators */
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{ 0x6c, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
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{ 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
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{ 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
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{ 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
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{ 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
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{ 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
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{ 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
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{ 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
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#endif
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static int etm_reg_arch_type = -1;
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@ -1180,6 +1180,7 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
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if (argc == 4)
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{
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/* what parts of data access are traced? */
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if (strcmp(args[0], "none") == 0)
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{
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tracemode = ETMV1_TRACE_NONE;
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@ -1248,6 +1249,12 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
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command_print(cmd_ctx, "invalid option '%s'", args[2]);
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return ERROR_OK;
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}
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/* IGNORED:
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* - CPRT tracing (coprocessor register transfers)
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* - debug request (causes debug entry on trigger)
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* - stall on FIFOFULL (preventing tracedata lossage)
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*/
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}
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else if (argc != 0)
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{
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