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Merge pull request #95 from riscv/memread 

Fix block memory reads on slow targets.
macbuild
Palmer Dabbelt 2017-08-25 16:57:07 -07:00 committed by GitHub
parent 4d0e88d887 0ff4103a26
commit 322669ca98
2 changed files with 37 additions and 12 deletions
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5
src/target/riscv/batch.c
View File

@ -44,6 +44,11 @@ bool riscv_batch_full(struct riscv_batch *batch)
void riscv_batch_run(struct riscv_batch *batch)
{
if (batch->used_scans == 0) {
LOG_DEBUG("Ignoring empty batch.");
return;
}
LOG_DEBUG("running a batch of %ld scans", (long)batch->used_scans);
riscv_batch_add_nop(batch);

44
src/target/riscv/riscv-013.c
View File

@ -1351,18 +1351,18 @@ static int read_memory(struct target *target, target_addr_t address,
riscv_addr_t cur_addr = 0xbadbeef;
riscv_addr_t fin_addr = address + (count * size);
riscv_addr_t prev_addr = ((riscv_addr_t) address) - size;
bool first = true;
bool ignore_prev_addr = true;
bool this_is_last_read = false;
LOG_DEBUG("reading until final address 0x%" PRIx64, fin_addr);
while (count > 1 && !this_is_last_read) {
cur_addr = riscv_read_debug_buffer_x(target, d_addr);
LOG_DEBUG("transferring burst starting at address 0x%" TARGET_PRIxADDR
" (previous burst was 0x%" TARGET_PRIxADDR ")", cur_addr,
prev_addr);
assert(first || prev_addr < cur_addr);
first = false;
prev_addr = cur_addr;
riscv_addr_t start = (cur_addr - address) / size;
LOG_DEBUG("reading burst at address 0x%" TARGET_PRIxADDR
"; prev_addr=0x%" TARGET_PRIxADDR "; start=0x%"
TARGET_PRIxADDR, cur_addr, prev_addr, start);
assert(ignore_prev_addr || prev_addr < cur_addr);
prev_addr = cur_addr;
ignore_prev_addr = false;
assert (cur_addr >= address);
struct riscv_batch *batch = riscv_batch_alloc(
target,
@ -1407,10 +1407,11 @@ static int read_memory(struct target *target, target_addr_t address,
info->cmderr = get_field(abstractcs, DMI_ABSTRACTCS_CMDERR);
switch (info->cmderr) {
case CMDERR_NONE:
LOG_DEBUG("successful (partial?) memory write");
LOG_DEBUG("successful (partial?) memory read");
break;
case CMDERR_BUSY:
LOG_DEBUG("memory write resulted in busy response");
LOG_DEBUG("memory read resulted in busy response; "
"this_is_last_read=%d", this_is_last_read);
riscv013_clear_abstract_error(target);
increase_ac_busy_delay(target);
retry_batch_transaction = true;
@ -1425,7 +1426,23 @@ static int read_memory(struct target *target, target_addr_t address,
riscv_batch_free(batch);
return ERROR_FAIL;
}
if (retry_batch_transaction) continue;
if (retry_batch_transaction) {
this_is_last_read = false;
ignore_prev_addr = true;
switch (riscv_xlen(target)) {
case 64:
riscv013_write_debug_buffer(target, d_addr + 4, (cur_addr - size) >> 32);
case 32:
riscv013_write_debug_buffer(target, d_addr, (cur_addr - size));
break;
default:
LOG_ERROR("unknown XLEN %d", riscv_xlen(target));
return ERROR_FAIL;
}
continue;
}
for (size_t i = start; i < start + reads; ++i) {
riscv_addr_t offset = size*i;
@ -1435,8 +1452,11 @@ static int read_memory(struct target *target, target_addr_t address,
if (this_is_last_read && i == start + reads - 1) {
riscv013_set_autoexec(target, d_data, 0);
// access debug buffer without executing a program - this address logic was taken from program.c
int const off = (r_data - riscv_debug_buffer_addr(program.target)) / sizeof(program.debug_buffer[0]);
// Access debug buffer without executing a program. This
// address logic was taken from program.c.
int const off = (r_data -
riscv_debug_buffer_addr(program.target)) /
sizeof(program.debug_buffer[0]);
value = riscv_read_debug_buffer(target, off);
} else {
uint64_t dmi_out = riscv_batch_get_dmi_read(batch, rereads);