David Brownell <david-b@pacbell.net> thumb2 disassembly for Load byte, memory hints
git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
oharboe
parent
c7565cc381
commit
31b520c379
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@ -2,6 +2,8 @@
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* Copyright (C) 2006 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* Copyright (C) 2009 by David Brownell *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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@ -3340,6 +3342,170 @@ static int t2ev_load_word(uint32_t opcode, uint32_t address,
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return ERROR_INVALID_ARGUMENTS;
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}
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static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
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arm_instruction_t *instruction, char *cp)
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{
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int rn = (opcode >> 16) & 0xf;
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int rt = (opcode >> 12) & 0xf;
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int op2 = (opcode >> 6) & 0x3f;
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unsigned immed;
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char *p1 = "]", *p2 = "";
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char *mnemonic;
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switch ((opcode >> 23) & 0x3) {
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case 0:
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if ((rn & rt) == 0xf) {
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preload_immediate_t2:
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immed = opcode & 0xfff;
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preload_immediate_t1:
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p1 = (opcode & (1 << 21)) ? "W" : "";
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sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
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p1, rn, immed, immed);
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return ERROR_OK;
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}
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if (rn == 0x0f && rt != 0x0f) {
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ldrb_literal:
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immed = opcode & 0xfff;
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address = thumb_alignpc4(address);
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if (opcode & (1 << 23))
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address += immed;
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else
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address -= immed;
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sprintf(cp, "LDRB\tr%d, %#8.8" PRIx32,
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rt, address);
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return ERROR_OK;
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}
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if (rn == 0x0f)
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break;
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if ((op2 & 0x3c) == 0x38) {
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immed = opcode & 0xff;
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sprintf(cp, "LDRBT\tr%d, [r%d, #%d]\t; %#2.2x",
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rt, rn, immed, immed);
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return ERROR_OK;
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}
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if ((op2 & 0x3c) == 0x30) {
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if (rt == 0x0f) {
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immed = opcode & 0xff;
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goto preload_immediate_t1;
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}
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mnemonic = "LDRB";
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ldrxb_immediate_t3:
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immed = opcode & 0xff;
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if (opcode & 0x200)
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immed = -immed;
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/* two indexed modes will write back rn */
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if (opcode & 0x100) {
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if (opcode & 0x400) /* pre-indexed */
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p2 = "]!";
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else { /* post-indexed */
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p1 = "]";
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p2 = "";
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}
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}
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ldrxb_immediate_t2:
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sprintf(cp, "%s\tr%d, [r%d%s, #%d%s\t; %#8.8x",
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mnemonic, rt, rn, p1,
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immed, p2, immed);
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return ERROR_OK;
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}
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if ((op2 & 0x24) == 0x24) {
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mnemonic = "LDRB";
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goto ldrxb_immediate_t3;
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}
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if (op2 == 0) {
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int rm = opcode & 0xf;
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if (rt == 0x0f)
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sprintf(cp, "PLD\t");
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else
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sprintf(cp, "LDRB.W\tr%d, ", rt);
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immed = (opcode >> 4) & 0x3;
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cp = strchr(cp, 0);
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sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
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return ERROR_OK;
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}
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break;
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case 1:
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if (rt == 0xf)
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goto preload_immediate_t2;
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if (rn == 0x0f)
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goto ldrb_literal;
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mnemonic = "LDRB.W";
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immed = opcode & 0xfff;
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goto ldrxb_immediate_t2;
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case 2:
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if ((rn & rt) == 0xf) {
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pli_immediate:
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immed = opcode & 0xfff;
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address = thumb_alignpc4(address);
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if (opcode & (1 << 23))
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address += immed;
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else
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address -= immed;
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sprintf(cp, "PLI\t%#8.8" PRIx32, address);
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return ERROR_OK;
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}
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if (rn == 0xf && rt != 0xf) {
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ldrsb_literal:
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immed = opcode & 0xfff;
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address = thumb_alignpc4(address);
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if (opcode & (1 << 23))
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address += immed;
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else
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address -= immed;
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sprintf(cp, "LDRSB\t%#8.8" PRIx32, address);
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return ERROR_OK;
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}
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if (rn == 0xf)
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break;
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if ((op2 & 0x3c) == 0x38) {
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immed = opcode & 0xff;
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sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %2.2x",
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rt, rn, immed, immed);
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return ERROR_OK;
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}
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if ((op2 & 0x3c) == 0x30) {
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if (rt == 0xf) {
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immed = opcode & 0xff;
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immed = -immed; // pli
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sprintf(cp, "PLI\t[r%d, #-%d]\t; %2.2x",
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rn, immed, immed);
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return ERROR_OK;
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}
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mnemonic = "LDRSB";
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goto ldrxb_immediate_t3;
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}
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if ((op2 & 0x24) == 0x24) {
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mnemonic = "LDRSB";
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goto ldrxb_immediate_t3;
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}
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if (op2 == 0) {
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int rm = opcode & 0xf;
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if (rt == 0x0f)
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sprintf(cp, "PLI\t");
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else
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sprintf(cp, "LDRSB.W\tr%d, ", rt);
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immed = (opcode >> 4) & 0x3;
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cp = strchr(cp, 0);
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sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
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return ERROR_OK;
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}
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break;
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case 3:
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if (rt == 0xf)
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goto pli_immediate;
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if (rn == 0xf)
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goto ldrsb_literal;
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immed = opcode & 0xfff;
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mnemonic = "LDRSB";
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goto ldrxb_immediate_t2;
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}
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return ERROR_INVALID_ARGUMENTS;
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}
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/*
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* REVISIT for Thumb2 instructions, instruction->type and friends aren't
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* always set. That means eventual arm_simulate_step() support for Thumb2
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@ -3407,6 +3573,10 @@ int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruc
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else if ((opcode & 0x1f700000) == 0x18500000)
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retval = t2ev_load_word(opcode, address, instruction, cp);
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/* ARMv7-M: A5.3.9 Load byte, memory hints */
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else if ((opcode & 0x1e700000) == 0x18100000)
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retval = t2ev_load_byte_hints(opcode, address, instruction, cp);
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/* ARMv7-M: A5.3.10 Store single data item */
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else if ((opcode & 0x1f100000) == 0x18000000)
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retval = t2ev_store_single(opcode, address, instruction, cp);
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