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tinyriscv-openocd
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- improved ETB trace output 

- use BKPT instruction on cores supporting it (ARM926EJ-S, ARM966E-S)
- correctly handle endianness of software breakpoint instruction


git-svn-id: svn://svn.berlios.de/openocd/trunk@143 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
drath 2007-04-26 14:41:27 +00:00
parent 22bc5194ae
commit 2f7eca4707
7 changed files with 42 additions and 13 deletions
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2
src/openocd.c
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@ -18,7 +18,7 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-04-25 22:15 CEST)"
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-04-26 16:40 CEST)"
#ifdef HAVE_CONFIG_H
#include "config.h"

6
src/target/arm7_9_common.c
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@ -187,15 +187,15 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
/* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
}
else
{
/* keep the original instruction in target endianness */
target->type->read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
target_write_u32(target, breakpoint->address, arm7_9->thumb_bkpt);
/* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
}
breakpoint->set = 1;
}

4
src/target/arm7tdmi.c
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@ -811,8 +811,8 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c
arm7_9->post_restore_context = NULL;
/* initialize arch-specific breakpoint handling */
buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
arm7_9->arm_bkpt = 0xdeeedeee;
arm7_9->thumb_bkpt = 0xdeee;
arm7_9->sw_bkpts_use_wp = 1;
arm7_9->sw_bkpts_enabled = 0;

4
src/target/arm926ejs.c
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@ -671,6 +671,10 @@ int arm926ejs_init_arch_info(target_t *target, arm926ejs_common_t *arm926ejs, in
/* The ARM926EJ-S implements the ARMv5TE architecture which
* has the BKPT instruction, so we don't have to use a watchpoint comparator
*/
arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
arm7_9->sw_bkpts_use_wp = 0;
arm7_9->sw_bkpts_enabled = 1;
return ERROR_OK;

10
src/target/arm966e.c
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@ -171,12 +171,22 @@ int arm966e_quit(void)
int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, int chain_pos, char *variant)
{
arm9tdmi_common_t *arm9tdmi = &arm966e->arm9tdmi_common;
arm7_9_common_t *arm7_9 = &arm9tdmi->arm7_9_common;
arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant);
arm9tdmi->arch_info = arm966e;
arm966e->common_magic = ARM966E_COMMON_MAGIC;
/* The ARM966E-S implements the ARMv5TE architecture which
* has the BKPT instruction, so we don't have to use a watchpoint comparator
*/
arm7_9->arm_bkpt = ARMV5_BKPT(0x0);
arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff;
arm7_9->sw_bkpts_use_wp = 0;
arm7_9->sw_bkpts_enabled = 1;
return ERROR_OK;
}

4
src/target/arm9tdmi.c
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@ -947,8 +947,8 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, int c
arm7_9->post_restore_context = NULL;
/* initialize arch-specific breakpoint handling */
buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
arm7_9->arm_bkpt = 0xdeeedeee;
arm7_9->thumb_bkpt = 0xdeee;
arm7_9->sw_bkpts_use_wp = 1;
arm7_9->sw_bkpts_enabled = 0;

25
src/target/etb.c
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@ -1,5 +1,5 @@
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Copyright (C) 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
@ -341,6 +341,8 @@ int handle_arm7_9_etb_dump_command(struct command_context_s *cmd_ctx, char *cmd,
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
int i;
int first_frame = 0;
int last_frame;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
@ -365,16 +367,29 @@ int handle_arm7_9_etb_dump_command(struct command_context_s *cmd_ctx, char *cmd,
arm7_9->etb->RAM_width = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
}
/* always start reading from the beginning of the buffer */
etb_write_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], 0x0);
for (i = 0; i < arm7_9->etb->RAM_depth; i++)
etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_STATUS]);
etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
/* check if we overflowed, and adjust first and last frame of the trace accordingly */
if (buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_STATUS].value, 1, 1))
{
first_frame = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
last_frame = first_frame - 1;
}
else
{
last_frame = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32) - 1;
}
etb_write_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
for (i = first_frame; (i % arm7_9->etb->RAM_depth) != last_frame; i++)
{
u32 trace_data;
etb_read_reg(&arm7_9->etb->reg_cache->reg_list[ETB_RAM_DATA]);
jtag_execute_queue();
trace_data = buf_get_u32(arm7_9->etb->reg_cache->reg_list[ETB_RAM_DATA].value, 0, 32);
command_print(cmd_ctx, "%8.8i: %i %2.2x %2.2x %2.2x (0x%8.8x)",
i, (trace_data >> 19) & 1, (trace_data >> 11) & 0xff, (trace_data >> 3) & 0xff, trace_data & 0x7, trace_data);
i % 2048, (trace_data >> 19) & 1, (trace_data >> 11) & 0xff, (trace_data >> 3) & 0xff, trace_data & 0x7, trace_data);
}
return ERROR_OK;