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- add missing svn props from previous commit 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1395 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
ntfreak 2009-03-02 12:51:42 +00:00
parent 623100d59d
commit 2f184a5008
5 changed files with 430 additions and 430 deletions
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512
src/flash/orion_nand.c
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@ -1,256 +1,256 @@
/*************************************************************************** /***************************************************************************
* Copyright (C) 2009 by Marvell Semiconductors, Inc. * * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
* Written by Nicolas Pitre <nico at marvell.com> * * Written by Nicolas Pitre <nico at marvell.com> *
* * * *
* This program is free software; you can redistribute it and/or modify * * This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by * * it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or * * the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. * * (at your option) any later version. *
* * * *
* This program is distributed in the hope that it will be useful, * * This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of * * but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. * * GNU General Public License for more details. *
* * * *
* You should have received a copy of the GNU General Public License * * You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the * * along with this program; if not, write to the *
* Free Software Foundation, Inc., * * Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/ ***************************************************************************/
/* /*
* NAND controller interface for Marvell Orion/Kirkwood SoCs. * NAND controller interface for Marvell Orion/Kirkwood SoCs.
*/ */
#ifdef HAVE_CONFIG_H #ifdef HAVE_CONFIG_H
#include "config.h" #include "config.h"
#endif #endif
#include "replacements.h" #include "replacements.h"
#include "log.h" #include "log.h"
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
#include "nand.h" #include "nand.h"
#include "target.h" #include "target.h"
#include "armv4_5.h" #include "armv4_5.h"
#include "binarybuffer.h" #include "binarybuffer.h"
typedef struct orion_nand_controller_s typedef struct orion_nand_controller_s
{ {
struct target_s *target; struct target_s *target;
working_area_t *copy_area; working_area_t *copy_area;
u32 cmd; u32 cmd;
u32 addr; u32 addr;
u32 data; u32 data;
} orion_nand_controller_t; } orion_nand_controller_t;
#define CHECK_HALTED \ #define CHECK_HALTED \
do { \ do { \
if (target->state != TARGET_HALTED) { \ if (target->state != TARGET_HALTED) { \
LOG_ERROR("NAND flash access requires halted target"); \ LOG_ERROR("NAND flash access requires halted target"); \
return ERROR_NAND_OPERATION_FAILED; \ return ERROR_NAND_OPERATION_FAILED; \
} \ } \
} while (0) } while (0)
int orion_nand_command(struct nand_device_s *device, u8 command) int orion_nand_command(struct nand_device_s *device, u8 command)
{ {
orion_nand_controller_t *hw = device->controller_priv; orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target; target_t *target = hw->target;
CHECK_HALTED; CHECK_HALTED;
target_write_u8(target, hw->cmd, command); target_write_u8(target, hw->cmd, command);
return ERROR_OK; return ERROR_OK;
} }
int orion_nand_address(struct nand_device_s *device, u8 address) int orion_nand_address(struct nand_device_s *device, u8 address)
{ {
orion_nand_controller_t *hw = device->controller_priv; orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target; target_t *target = hw->target;
CHECK_HALTED; CHECK_HALTED;
target_write_u8(target, hw->addr, address); target_write_u8(target, hw->addr, address);
return ERROR_OK; return ERROR_OK;
} }
int orion_nand_read(struct nand_device_s *device, void *data) int orion_nand_read(struct nand_device_s *device, void *data)
{ {
orion_nand_controller_t *hw = device->controller_priv; orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target; target_t *target = hw->target;
CHECK_HALTED; CHECK_HALTED;
target_read_u8(target, hw->data, data); target_read_u8(target, hw->data, data);
return ERROR_OK; return ERROR_OK;
} }
int orion_nand_write(struct nand_device_s *device, u16 data) int orion_nand_write(struct nand_device_s *device, u16 data)
{ {
orion_nand_controller_t *hw = device->controller_priv; orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target; target_t *target = hw->target;
CHECK_HALTED; CHECK_HALTED;
target_write_u8(target, hw->data, data); target_write_u8(target, hw->data, data);
return ERROR_OK; return ERROR_OK;
} }
int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size) int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
{ {
while (size--) while (size--)
orion_nand_write(device, *data++); orion_nand_write(device, *data++);
return ERROR_OK; return ERROR_OK;
} }
int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size) int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
{ {
orion_nand_controller_t *hw = device->controller_priv; orion_nand_controller_t *hw = device->controller_priv;
target_t *target = hw->target; target_t *target = hw->target;
armv4_5_algorithm_t algo; armv4_5_algorithm_t algo;
reg_param_t reg_params[3]; reg_param_t reg_params[3];
u32 target_buf; u32 target_buf;
int retval; int retval;
static const u32 code[] = { static const u32 code[] = {
0xe4d13001, /* ldrb r3, [r1], #1 */ 0xe4d13001, /* ldrb r3, [r1], #1 */
0xe5c03000, /* strb r3, [r0] */ 0xe5c03000, /* strb r3, [r0] */
0xe2522001, /* subs r2, r2, #1 */ 0xe2522001, /* subs r2, r2, #1 */
0x1afffffb, /* bne 0 */ 0x1afffffb, /* bne 0 */
0xeafffffe, /* b . */ 0xeafffffe, /* b . */
}; };
int code_size = sizeof(code); int code_size = sizeof(code);
if (!hw->copy_area) { if (!hw->copy_area) {
u8 code_buf[code_size]; u8 code_buf[code_size];
int i; int i;
/* make sure we have a working area */ /* make sure we have a working area */
if (target_alloc_working_area(target, if (target_alloc_working_area(target,
code_size + device->page_size, code_size + device->page_size,
&hw->copy_area) != ERROR_OK) &hw->copy_area) != ERROR_OK)
{ {
return orion_nand_slow_block_write(device, data, size); return orion_nand_slow_block_write(device, data, size);
} }
/* copy target instructions to target endianness */ /* copy target instructions to target endianness */
for (i = 0; i < code_size/4; i++) for (i = 0; i < code_size/4; i++)
target_buffer_set_u32(target, code_buf + i*4, code[i]); target_buffer_set_u32(target, code_buf + i*4, code[i]);
/* write code to working area */ /* write code to working area */
retval = target->type->write_memory(target, retval = target->type->write_memory(target,
hw->copy_area->address, hw->copy_area->address,
4, code_size/4, code_buf); 4, code_size/4, code_buf);
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
} }
/* copy data to target's memory */ /* copy data to target's memory */
target_buf = hw->copy_area->address + code_size; target_buf = hw->copy_area->address + code_size;
retval = target->type->bulk_write_memory(target, target_buf, retval = target->type->bulk_write_memory(target, target_buf,
size/4, data); size/4, data);
if (retval == ERROR_OK && size & 3) { if (retval == ERROR_OK && size & 3) {
retval = target->type->write_memory(target, retval = target->type->write_memory(target,
target_buf + (size & ~3), target_buf + (size & ~3),
1, size & 3, data + (size & ~3)); 1, size & 3, data + (size & ~3));
} }
if (retval != ERROR_OK) if (retval != ERROR_OK)
return retval; return retval;
algo.common_magic = ARMV4_5_COMMON_MAGIC; algo.common_magic = ARMV4_5_COMMON_MAGIC;
algo.core_mode = ARMV4_5_MODE_SVC; algo.core_mode = ARMV4_5_MODE_SVC;
algo.core_state = ARMV4_5_STATE_ARM; algo.core_state = ARMV4_5_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_IN); init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
init_reg_param(&reg_params[1], "r1", 32, PARAM_IN); init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
init_reg_param(&reg_params[2], "r2", 32, PARAM_IN); init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
buf_set_u32(reg_params[0].value, 0, 32, hw->data); buf_set_u32(reg_params[0].value, 0, 32, hw->data);
buf_set_u32(reg_params[1].value, 0, 32, target_buf); buf_set_u32(reg_params[1].value, 0, 32, target_buf);
buf_set_u32(reg_params[2].value, 0, 32, size); buf_set_u32(reg_params[2].value, 0, 32, size);
retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
hw->copy_area->address, hw->copy_area->address,
hw->copy_area->address + code_size - 4, hw->copy_area->address + code_size - 4,
1000, &algo); 1000, &algo);
if (retval != ERROR_OK) if (retval != ERROR_OK)
LOG_ERROR("error executing hosted NAND write"); LOG_ERROR("error executing hosted NAND write");
destroy_reg_param(&reg_params[0]); destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]); destroy_reg_param(&reg_params[1]);
destroy_reg_param(&reg_params[2]); destroy_reg_param(&reg_params[2]);
return retval; return retval;
} }
int orion_nand_reset(struct nand_device_s *device) int orion_nand_reset(struct nand_device_s *device)
{ {
return orion_nand_command(device, NAND_CMD_RESET); return orion_nand_command(device, NAND_CMD_RESET);
} }
int orion_nand_controller_ready(struct nand_device_s *device, int timeout) int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
{ {
return 1; return 1;
} }
int orion_nand_register_commands(struct command_context_s *cmd_ctx) int orion_nand_register_commands(struct command_context_s *cmd_ctx)
{ {
return ERROR_OK; return ERROR_OK;
} }
int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
char **args, int argc, char **args, int argc,
struct nand_device_s *device) struct nand_device_s *device)
{ {
orion_nand_controller_t *hw; orion_nand_controller_t *hw;
u32 base; u32 base;
u8 ale, cle; u8 ale, cle;
if (argc != 3) { if (argc != 3) {
LOG_ERROR("arguments must be: <target_number> <NAND_address>\n"); LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
return ERROR_NAND_DEVICE_INVALID; return ERROR_NAND_DEVICE_INVALID;
} }
hw = calloc(1, sizeof(*hw)); hw = calloc(1, sizeof(*hw));
if (!hw) { if (!hw) {
LOG_ERROR("no memory for nand controller\n"); LOG_ERROR("no memory for nand controller\n");
return ERROR_NAND_DEVICE_INVALID; return ERROR_NAND_DEVICE_INVALID;
} }
device->controller_priv = hw; device->controller_priv = hw;
hw->target = get_target_by_num(strtoul(args[1], NULL, 0)); hw->target = get_target_by_num(strtoul(args[1], NULL, 0));
if (!hw->target) { if (!hw->target) {
LOG_ERROR("no target '%s' configured", args[1]); LOG_ERROR("no target '%s' configured", args[1]);
free(hw); free(hw);
return ERROR_NAND_DEVICE_INVALID; return ERROR_NAND_DEVICE_INVALID;
} }
base = strtoul(args[2], NULL, 0); base = strtoul(args[2], NULL, 0);
cle = 0; cle = 0;
ale = 1; ale = 1;
hw->data = base; hw->data = base;
hw->cmd = base + (1 << cle); hw->cmd = base + (1 << cle);
hw->addr = base + (1 << ale); hw->addr = base + (1 << ale);
return ERROR_OK; return ERROR_OK;
} }
int orion_nand_init(struct nand_device_s *device) int orion_nand_init(struct nand_device_s *device)
{ {
return ERROR_OK; return ERROR_OK;
} }
nand_flash_controller_t orion_nand_controller = nand_flash_controller_t orion_nand_controller =
{ {
.name = "orion", .name = "orion",
.command = orion_nand_command, .command = orion_nand_command,
.address = orion_nand_address, .address = orion_nand_address,
.read_data = orion_nand_read, .read_data = orion_nand_read,
.write_data = orion_nand_write, .write_data = orion_nand_write,
.write_block_data = orion_nand_fast_block_write, .write_block_data = orion_nand_fast_block_write,
.reset = orion_nand_reset, .reset = orion_nand_reset,
.controller_ready = orion_nand_controller_ready, .controller_ready = orion_nand_controller_ready,
.nand_device_command = orion_nand_device_command, .nand_device_command = orion_nand_device_command,
.register_commands = orion_nand_register_commands, .register_commands = orion_nand_register_commands,
.init = orion_nand_init, .init = orion_nand_init,
}; };

222
src/target/board/sheevaplug.cfg
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@ -1,111 +1,111 @@
# Marvell SheevaPlug # Marvell SheevaPlug
source [find interface/sheevaplug.cfg] source [find interface/sheevaplug.cfg]
source [find target/feroceon.cfg] source [find target/feroceon.cfg]
$_TARGETNAME configure -event reset-init { sheevaplug_init } $_TARGETNAME configure -event reset-init { sheevaplug_init }
$_TARGETNAME configure \ $_TARGETNAME configure \
-work-area-phys 0x10000000 \ -work-area-phys 0x10000000 \
-work-area-size 65536 \ -work-area-size 65536 \
-work-area-backup 0 -work-area-backup 0
arm7_9 dcc_downloads enable arm7_9 dcc_downloads enable
# this assumes the hardware default peripherals location before u-Boot moves it # this assumes the hardware default peripherals location before u-Boot moves it
nand device orion 0 0xd8000000 nand device orion 0 0xd8000000
proc sheevaplug_init { } { proc sheevaplug_init { } {
arm926ejs cp15 0 0 1 0 0x00052078 arm926ejs cp15 0 0 1 0 0x00052078
mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
mww 0xD0001404 0x39543000 # Dunit Control Low Register mww 0xD0001404 0x39543000 # Dunit Control Low Register
mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register
mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register
mww 0xD0001424 0x0000F17F # Dunit Control High Register mww 0xD0001424 0x0000F17F # Dunit Control High Register
mww 0xD0001428 0x00085520 # Dunit Control High Register mww 0xD0001428 0x00085520 # Dunit Control High Register
mww 0xD000147c 0x00008552 # Dunit Control High Register mww 0xD000147c 0x00008552 # Dunit Control High Register
mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
mww 0xD0001508 0x10000000 # CS1n Base Register mww 0xD0001508 0x10000000 # CS1n Base Register
mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
mww 0xD0001514 0x00000000 # CS2n Size Register mww 0xD0001514 0x00000000 # CS2n Size Register
mww 0xD000151C 0x00000000 # CS3n Size Register mww 0xD000151C 0x00000000 # CS3n Size Register
mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register
mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register
mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0020204 0x00000000 # " mww 0xD0020204 0x00000000 # "
mww 0xD0010000 0x01111111 # MPP 0 to 7 mww 0xD0010000 0x01111111 # MPP 0 to 7
mww 0xD0010004 0x11113322 # MPP 8 to 15 mww 0xD0010004 0x11113322 # MPP 8 to 15
mww 0xD0010008 0x00001111 # MPP 16 to 23 mww 0xD0010008 0x00001111 # MPP 16 to 23
mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
mww 0xD0010470 0x01C7D943 # NAND Flash Control Register mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
} }
proc sheevaplug_reflash_uboot { } { proc sheevaplug_reflash_uboot { } {
# reflash the u-Boot binary # reflash the u-Boot binary
#reset init #reset init
nand probe 0 nand probe 0
nand erase 0 0 4 nand erase 0 0 4
nand write 0 uboot.bin 0 nand write 0 uboot.bin 0
reset run reset run
} }
proc sheevaplug_load_uboot { } { proc sheevaplug_load_uboot { } {
# load u-Boot into RAM # load u-Boot into RAM
#reset init #reset init
load_image /tmp/uboot.elf load_image /tmp/uboot.elf
verify_image uboot.elf verify_image uboot.elf
resume 0x00600000 resume 0x00600000
} }

8
src/target/interface/sheevaplug.cfg
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@ -1,4 +1,4 @@
interface ft2232 interface ft2232
ft2232_layout sheevaplug ft2232_layout sheevaplug
ft2232_vid_pid 0x0403 0x6010 ft2232_vid_pid 0x0403 0x6010
jtag_khz 3000 jtag_khz 3000

60
src/target/target/feroceon.cfg
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@ -1,30 +1,30 @@
###################################### ######################################
# Target: Marvell Feroceon CPU core # Target: Marvell Feroceon CPU core
###################################### ######################################
if { [info exists CHIPNAME] } { if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME set _CHIPNAME $CHIPNAME
} else { } else {
set _CHIPNAME feroceon set _CHIPNAME feroceon
} }
if { [info exists ENDIAN] } { if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN set _ENDIAN $ENDIAN
} else { } else {
set _ENDIAN little set _ENDIAN little
} }
if { [info exists CPUTAPID ] } { if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID set _CPUTAPID $CPUTAPID
} else { } else {
set _CPUTAPID 0x20a023d3 set _CPUTAPID 0x20a023d3
} }
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME [format "%s.cpu" $_CHIPNAME] set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst reset_config trst_and_srst
jtag_nsrst_delay 200 jtag_nsrst_delay 200
jtag_ntrst_delay 200 jtag_ntrst_delay 200

58
src/target/test/syntax1.cfg
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@ -1,29 +1,29 @@
jtag_nsrst_delay 200 jtag_nsrst_delay 200
jtag_ntrst_delay 200 jtag_ntrst_delay 200
#use combined on interfaces or targets that can't set TRST/SRST separately #use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst reset_config trst_and_srst srst_pulls_trst
#LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough #LPCs need reset pulled while RTCK is low. 0 to activate JTAG, power-on reset is not enough
jtag_reset 1 1 jtag_reset 1 1
jtag_reset 0 0 jtag_reset 0 0
#jtag scan chain #jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f jtag newtap lpc2148 one -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4f1f0f0f
#target configuration #target configuration
#daemon_startup reset #daemon_startup reset
set _TARGETNAME [format "%s.cpu" lpc2148] set _TARGETNAME [format "%s.cpu" lpc2148]
target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-virt 0 -work-area-backup 0 target create lpc2148.cpu arm7tdmi -endian little -work-area-size 0x4000 -work-area-phys 0x40000000 -work-area-virt 0 -work-area-backup 0
$_TARGETNAME configure -event reset-init { $_TARGETNAME configure -event reset-init {
soft_reset_halt soft_reset_halt
mvb 0xE01FC040 0x01 mvb 0xE01FC040 0x01
} }
flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765