armv4_5_core_reg_t -> struct armv4_5_core_reg
Remove misleading typedef and redundant suffix from struct armv4_5_core_reg.__archive__
parent
15e8e45308
commit
2dd9c5e1da
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@ -1600,7 +1600,7 @@ int arm7_9_restore_context(target_t *target)
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struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
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struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
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reg_t *reg;
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armv4_5_core_reg_t *reg_arch_info;
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struct armv4_5_core_reg *reg_arch_info;
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enum armv4_5_mode current_mode = armv4_5->core_mode;
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int i, j;
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int dirty;
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@ -2114,7 +2114,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
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enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
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if ((num < 0) || (num > 16))
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return ERROR_INVALID_ARGUMENTS;
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@ -2144,7 +2144,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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/* read a program status register
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* if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
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*/
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armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
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struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
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int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
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arm7_9->read_xpsr(target, &value, spsr);
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@ -2178,7 +2178,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
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enum armv4_5_mode reg_mode = ((struct armv4_5_core_reg*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
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if ((num < 0) || (num > 16))
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return ERROR_INVALID_ARGUMENTS;
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@ -2207,7 +2207,7 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
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/* write a program status register
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* if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
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*/
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armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
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struct armv4_5_core_reg *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
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int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
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/* if we're writing the CPSR, mask the T bit */
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@ -80,7 +80,7 @@ char* armv4_5_state_strings[] =
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int armv4_5_core_reg_arch_type = -1;
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armv4_5_core_reg_t armv4_5_core_reg_list_arch_info[] =
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struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
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{
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{0, ARMV4_5_MODE_ANY, NULL, NULL},
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{1, ARMV4_5_MODE_ANY, NULL, NULL},
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@ -170,7 +170,7 @@ reg_t armv4_5_gdb_dummy_fps_reg =
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int armv4_5_get_core_reg(reg_t *reg)
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{
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int retval;
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armv4_5_core_reg_t *armv4_5 = reg->arch_info;
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struct armv4_5_core_reg *armv4_5 = reg->arch_info;
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target_t *target = armv4_5->target;
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if (target->state != TARGET_HALTED)
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@ -187,7 +187,7 @@ int armv4_5_get_core_reg(reg_t *reg)
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int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
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{
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armv4_5_core_reg_t *armv4_5 = reg->arch_info;
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struct armv4_5_core_reg *armv4_5 = reg->arch_info;
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target_t *target = armv4_5->target;
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struct armv4_5_common_s *armv4_5_target = target_to_armv4_5(target);
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uint32_t value = buf_get_u32(buf, 0, 32);
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@ -254,7 +254,7 @@ reg_cache_t* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5
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int num_regs = 37;
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reg_cache_t *cache = malloc(sizeof(reg_cache_t));
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reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
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armv4_5_core_reg_t *arch_info = malloc(sizeof(armv4_5_core_reg_t) * num_regs);
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struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
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int i;
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cache->name = "arm v4/5 registers";
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@ -127,13 +127,13 @@ struct armv4_5_algorithm
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enum armv4_5_state core_state;
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};
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typedef struct armv4_5_core_reg_s
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struct armv4_5_core_reg
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{
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int num;
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enum armv4_5_mode mode;
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target_t *target;
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armv4_5_common_t *armv4_5_common;
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} armv4_5_core_reg_t;
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};
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reg_cache_t* armv4_5_build_reg_cache(target_t *target,
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armv4_5_common_t *armv4_5_common);
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