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tinyriscv-openocd
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Make this compile for 32-bit targets.

__archive__
Tim Newsome 2016-06-15 11:48:13 -07:00
parent aaa8ce10b8
commit 2d02e77bed
1 changed files with 4 additions and 4 deletions
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8
src/target/riscv/riscv.c
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@ -74,8 +74,8 @@ typedef enum {
/*** Debug Bus registers. ***/
#define DMCONTROL 0x10
#define DMCONTROL_INTERRUPT (1L<<33)
#define DMCONTROL_HALTNOT (1L<<32)
#define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
#define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
#define DMCONTROL_BUSERROR (7<<19)
#define DMCONTROL_SERIAL (3<<16)
#define DMCONTROL_AUTOINCREMENT (1<<15)
@ -307,8 +307,8 @@ static void dbus_write(struct target *target, uint16_t address, uint64_t value)
status = dbus_scan(target, NULL, DBUS_OP_WRITE, address, value);
}
if (status != DBUS_STATUS_SUCCESS) {
LOG_ERROR("dbus_write failed write 0x%lx to 0x%x; status=%d\n", value,
address, status);
LOG_ERROR("dbus_write failed write 0x%" PRIx64 " to 0x%x; status=%d\n",
value, address, status);
}
}