zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cfg: update for target's that support cortex_m AIRCR SYSRESETREQ 

If the target supports SYSRESETREQ make sure we use that as the default
if srst is not fitted/configured.

Change-Id: I24c907493134506320e69c1218702930629c1cdc
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/792
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
__archive__
Spencer Oliver 2012-08-23 21:03:29 +01:00 committed by Freddie Chopin
parent 4be685c616
commit 2ce4e31bbc
7 changed files with 29 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
tcl/target/at91sam3XXX.cfg
View File

@ -66,3 +66,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-ar
$_TARGETNAME configure -event gdb-flash-erase-start { $_TARGETNAME configure -event gdb-flash-erase-start {
halt halt
} }
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m3 reset_config sysresetreq

5
tcl/target/at91sam3nXX.cfg
View File

@ -22,3 +22,8 @@ target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash set _FLASHNAME $_CHIPNAME.flash
flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m3 reset_config sysresetreq

4
tcl/target/at91sam4XXX.cfg
View File

@ -43,3 +43,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-ar
$_TARGETNAME configure -event gdb-flash-erase-start { $_TARGETNAME configure -event gdb-flash-erase-start {
halt halt
} }
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m3 reset_config sysresetreq

4
tcl/target/k40.cfg
View File

@ -33,3 +33,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; } $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; } $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m3 reset_config sysresetreq

4
tcl/target/k60.cfg
View File

@ -33,3 +33,7 @@ target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu
$_CHIPNAME.cpu configure -event examine-start { puts "START..." ; } $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; }
$_CHIPNAME.cpu configure -event examine-end { puts "END..." ; } $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; }
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m3 reset_config sysresetreq

4
tcl/target/lpc17xx.cfg
View File

@ -91,3 +91,7 @@ $_TARGETNAME configure -event reset-init {
mww 0x400FC040 0x01 mww 0x400FC040 0x01
} }
# if srst is not fitted use VECTRESET to
# perform a soft reset - SYSRESETREQ is not supported
cortex_m3 reset_config vectreset

4
tcl/target/lpc4350.cfg
View File

@ -42,3 +42,7 @@ jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4 target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0 target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m3 reset_config sysresetreq