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- only if "reset halt" or "reset init" are issued will the reset vector be set up 

- If communication fails during assert between assert/deassert and during
assert, warnings are printed. The warning suggests using srst_only if the
clock locks up as that would allow the reset vector to be set up before
asserting reset.

git-svn-id: svn://svn.berlios.de/openocd/trunk@544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
oharboe 2008-04-07 10:48:44 +00:00
parent a2c45daf78
commit 2b7504c279
2 changed files with 39 additions and 22 deletions
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10
src/target/arm7_9_common.c
View File

@ -736,7 +736,7 @@ int arm7_9_poll(target_t *target)
/*
Some -S targets (ARM966E-S in the STR912 isn't affected, ARM926EJ-S
in the LPC3180 and AT91SAM9260 is affected) completely stop the JTAG clock
while the core is held in reset. It isn't possible to program the halt
while the core is held in reset(SRST). It isn't possible to program the halt
condition once reset was asserted, hence a hook that allows the target to set
up its reset-halt condition prior to asserting reset.
*/
@ -753,11 +753,13 @@ int arm7_9_assert_reset(target_t *target)
return ERROR_FAIL;
}
if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
{
/*
* Some targets do not support communication while TRST is asserted. We need to
* Some targets do not support communication while SRST is asserted. We need to
* set up the reset vector catch here.
*
* If TRST is in use, then these settings will be reset anyway, so setting them
* If TRST is asserted, then these settings will be reset anyway, so setting them
* here is harmless.
*/
if (arm7_9->has_vector_catch)
@ -773,12 +775,12 @@ int arm7_9_assert_reset(target_t *target)
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x100);
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xf7);
}
}
/* we can't know what state the target is in as we might e.g.
* be resetting after a power dropout, so we need to issue a tms/srst
*/
/* assert SRST and TRST */
/* system would get ouf sync if we didn't reset test-logic, too */
jtag_add_reset(1, 1);

19
src/target/target.c
View File

@ -297,7 +297,11 @@ int target_process_reset(struct command_context_s *cmd_ctx)
target->type->assert_reset(target);
target = target->next;
}
jtag_execute_queue();
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_WARNING("JTAG communication failed asserting reset.");
retval = ERROR_OK;
}
/* request target halt if necessary, and schedule further action */
target = targets;
@ -330,13 +334,24 @@ int target_process_reset(struct command_context_s *cmd_ctx)
target = target->next;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_WARNING("JTAG communication failed while reset was asserted. Consider using srst_only for reset_config.");
retval = ERROR_OK;
}
target = targets;
while (target)
{
target->type->deassert_reset(target);
target = target->next;
}
jtag_execute_queue();
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_WARNING("JTAG communication failed while deasserting reset.");
retval = ERROR_OK;
}
LOG_DEBUG("Waiting for halted stated as approperiate");