rtos: fix xml register support regression
Seems that when xml register support was added the rtos code was not updated to match. This then caused gdb to return the following error when rtos support was enabled - "Remote 'g' packet reply is too long". Change-Id: I7429c4b1efed120e2e690678d55f3d6e87ee1ff1 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2054 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>__archive__
Spencer Oliver
Paul Fertser
parent
f7ffd142ee
commit
27b073a941
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@ -26,8 +26,9 @@
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#endif
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#include "rtos.h"
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#include "target/armv7m.h"
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static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[] = {
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static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ -1, 32 }, /* r0 */
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{ -1, 32 }, /* r1 */
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{ -1, 32 }, /* r2 */
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@ -44,22 +45,13 @@ static const struct stack_register_offset rtos_chibios_arm_v7m_stack_offsets[] =
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{ -2, 32 }, /* sp */
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{ -1, 32 }, /* lr */
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{ 0x20, 32 }, /* pc */
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{ -1, 96 }, /* FPA1 */
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{ -1, 96 }, /* FPA2 */
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{ -1, 96 }, /* FPA3 */
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{ -1, 96 }, /* FPA4 */
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{ -1, 96 }, /* FPA5 */
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{ -1, 96 }, /* FPA6 */
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{ -1, 96 }, /* FPA7 */
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{ -1, 96 }, /* FPA8 */
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{ -1, 32 }, /* FPS */
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{ -1, 32 }, /* xPSR */
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};
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const struct rtos_register_stacking rtos_chibios_arm_v7m_stacking = {
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0x24, /* stack_registers_size */
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-1, /* stack_growth_direction */
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26, /* num_output_registers */
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0, /* stack_alignment */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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0, /* stack_alignment */
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rtos_chibios_arm_v7m_stack_offsets /* register_offsets */
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};
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@ -21,8 +21,9 @@
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#endif
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#include "rtos.h"
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#include "target/armv7m.h"
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static const struct stack_register_offset rtos_eCos_Cortex_M3_stack_offsets[] = {
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static const struct stack_register_offset rtos_eCos_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ 0x0c, 32 }, /* r0 */
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{ 0x10, 32 }, /* r1 */
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{ 0x14, 32 }, /* r2 */
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@ -39,22 +40,13 @@ static const struct stack_register_offset rtos_eCos_Cortex_M3_stack_offsets[] =
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{ -2, 32 }, /* sp */
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{ -1, 32 }, /* lr */
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{ 0x40, 32 }, /* pc */
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{ -1, 96 }, /* FPA1 */
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{ -1, 96 }, /* FPA2 */
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{ -1, 96 }, /* FPA3 */
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{ -1, 96 }, /* FPA4 */
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{ -1, 96 }, /* FPA5 */
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{ -1, 96 }, /* FPA6 */
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{ -1, 96 }, /* FPA7 */
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{ -1, 96 }, /* FPA8 */
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{ -1, 32 }, /* FPS */
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{ -1, 32 }, /* xPSR */
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};
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const struct rtos_register_stacking rtos_eCos_Cortex_M3_stacking = {
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0x44, /* stack_registers_size */
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-1, /* stack_growth_direction */
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26, /* num_output_registers */
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8, /* stack_alignment */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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8, /* stack_alignment */
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rtos_eCos_Cortex_M3_stack_offsets /* register_offsets */
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};
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@ -23,8 +23,9 @@
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#endif
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#include "rtos.h"
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#include "target/armv7m.h"
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static const struct stack_register_offset rtos_embkernel_Cortex_M_stack_offsets[] = {
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static const struct stack_register_offset rtos_embkernel_Cortex_M_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ 0x24, 32 }, /* r0 */
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{ 0x28, 32 }, /* r1 */
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{ 0x2c, 32 }, /* r2 */
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@ -41,23 +42,14 @@ static const struct stack_register_offset rtos_embkernel_Cortex_M_stack_offsets[
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{ -2, 32 }, /* sp */
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{ 0x38, 32 }, /* lr */
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{ 0x3c, 32 }, /* pc */
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{ -1, 96 }, /* FPA1 */
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{ -1, 96 }, /* FPA2 */
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{ -1, 96 }, /* FPA3 */
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{ -1, 96 }, /* FPA4 */
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{ -1, 96 }, /* FPA5 */
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{ -1, 96 }, /* FPA6 */
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{ -1, 96 }, /* FPA7 */
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{ -1, 96 }, /* FPA8 */
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{ -1, 32 }, /* FPS */
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{ 0x40, 32 }, /* xPSR */
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};
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const struct rtos_register_stacking rtos_embkernel_Cortex_M_stacking = {
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0x40, /* stack_registers_size */
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-1, /* stack_growth_direction */
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26, /* num_output_registers */
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8, /* stack_alignment */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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8, /* stack_alignment */
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rtos_embkernel_Cortex_M_stack_offsets /* register_offsets */
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};
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@ -23,8 +23,9 @@
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#endif
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#include "rtos.h"
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#include "target/armv7m.h"
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static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[] = {
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static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
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{ 0x20, 32 }, /* r0 */
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{ 0x24, 32 }, /* r1 */
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{ 0x28, 32 }, /* r2 */
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@ -41,19 +42,9 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[
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{ -2, 32 }, /* sp */
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{ 0x34, 32 }, /* lr */
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{ 0x38, 32 }, /* pc */
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{ -1, 96 }, /* FPA1 */
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{ -1, 96 }, /* FPA2 */
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{ -1, 96 }, /* FPA3 */
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{ -1, 96 }, /* FPA4 */
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{ -1, 96 }, /* FPA5 */
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{ -1, 96 }, /* FPA6 */
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{ -1, 96 }, /* FPA7 */
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{ -1, 96 }, /* FPA8 */
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{ -1, 32 }, /* FPS */
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{ 0x3c, 32 }, /* xPSR */
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};
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static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
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{ 0x08, 32 }, /* r0 (a1) */
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{ 0x0c, 32 }, /* r1 (a2) */
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@ -124,15 +115,14 @@ static const struct stack_register_offset rtos_standard_NDS32_N1068_stack_offset
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const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
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0x40, /* stack_registers_size */
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-1, /* stack_growth_direction */
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26, /* num_output_registers */
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8, /* stack_alignment */
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-1, /* stack_growth_direction */
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ARMV7M_NUM_CORE_REGS, /* num_output_registers */
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8, /* stack_alignment */
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rtos_standard_Cortex_M3_stack_offsets /* register_offsets */
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};
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const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
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0x48, /* stack_registers_size */
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0x48, /* stack_registers_size */
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-1, /* stack_growth_direction */
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26, /* num_output_registers */
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8, /* stack_alignment */
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@ -140,7 +130,7 @@ const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
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};
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const struct rtos_register_stacking rtos_standard_NDS32_N1068_stacking = {
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0x90, /* stack_registers_size */
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0x90, /* stack_registers_size */
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-1, /* stack_growth_direction */
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32, /* num_output_registers */
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8, /* stack_alignment */
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