flash: at91samd: flash write code cleaning
SAMD driver suffered from following problems: 1) Flash was erased as an integral part of flash write. It was not documented so with usual workflow it resulted in erasing flash twice (and reducing flash lifespan) and in almost double flashing time. 2) Sector erase was silently skipped if "is_erased" flag was set. "is_erased" logic was not reliable, e.g. when a row write was aborted after successful write of some pages, sector was still considered as erased. "is_erased" flag could not cope with flash writes from a user program. 3) Writing of a block with start address unaligned to a flash page resulted in failed assert and OpenOCD abort. 4) Disabling cache in bit 18 of 16-bit halfword never worked. MCU implements cache invalidate in hardware so there is no need to take care about. This bug was reported by Tony DiCola. New code does not erase flash in write operation. Instead it traditionally relies on erasing flash beforehand. "is_erased" logic and cache disabling is completely removed. It simplifies write procedure a lot and flash write is now faster. The change partly solves ticket #109 SAMD/SAM4L driver doubles flash erase. Change-Id: I582b497d01a351575533a1f8c9810a4413be0216 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3045 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>__archive__
Tomas Vanek
Spencer Oliver
parent
b5fa1e4d77
commit
26a65f4f13
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@ -255,7 +255,6 @@ struct samd_info {
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int num_pages;
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int sector_size;
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bool manual_wp;
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bool probed;
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struct target *target;
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struct samd_info *next;
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@ -384,9 +383,6 @@ static int samd_probe(struct flash_bank *bank)
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samd_protect_check(bank);
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/* By default we do not need to send page write commands */
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chip->manual_wp = false;
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/* Done */
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chip->probed = true;
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@ -433,35 +429,16 @@ static bool samd_check_error(struct target *target)
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static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
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{
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int res;
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/* Read current configuration. */
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uint16_t tmp = 0;
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int res = target_read_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB,
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&tmp);
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if (res != ERROR_OK)
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return res;
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/* Set cache disable. */
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res = target_write_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB,
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tmp | (1<<18));
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if (res != ERROR_OK)
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return res;
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/* Issue the NVM command */
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int res_cmd = target_write_u16(target,
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res = target_write_u16(target,
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SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
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/* Try to restore configuration, regardless of NVM command write
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* status. */
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res = target_write_u16(target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, tmp);
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if (res_cmd != ERROR_OK)
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return res_cmd;
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if (res != ERROR_OK)
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return res;
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@ -671,7 +648,6 @@ static int samd_erase(struct flash_bank *bank, int first, int last)
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (bank->sectors[s].is_erased != 1) {
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/* For each row in that sector */
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for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
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res = samd_erase_row(bank->target, r * chip->page_size * 4);
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@ -680,123 +656,11 @@ static int samd_erase(struct flash_bank *bank, int first, int last)
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return res;
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}
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}
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bank->sectors[s].is_erased = 1;
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}
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}
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return ERROR_OK;
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}
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static struct flash_sector *samd_find_sector_by_address(struct flash_bank *bank, uint32_t address)
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{
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struct samd_info *chip = (struct samd_info *)bank->driver_priv;
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for (int i = 0; i < bank->num_sectors; i++) {
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if (bank->sectors[i].offset <= address &&
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address < bank->sectors[i].offset + chip->sector_size)
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return &bank->sectors[i];
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}
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return NULL;
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}
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/* Write an entire row (four pages) from host buffer 'buf' to row-aligned
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* 'address' in the Flash. */
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static int samd_write_row(struct flash_bank *bank, uint32_t address,
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const uint8_t *buf)
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{
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int res;
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struct samd_info *chip = (struct samd_info *)bank->driver_priv;
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struct flash_sector *sector = samd_find_sector_by_address(bank, address);
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if (!sector) {
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LOG_ERROR("Can't find sector corresponding to address 0x%08" PRIx32, address);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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if (sector->is_protected) {
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LOG_ERROR("Trying to write to a protected sector at 0x%08" PRIx32, address);
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return ERROR_FLASH_OPERATION_FAILED;
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}
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/* Erase the row that we'll be writing to */
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res = samd_erase_row(bank->target, address);
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if (res != ERROR_OK)
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return res;
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/* Now write the pages in this row. */
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for (unsigned int i = 0; i < 4; i++) {
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bool error;
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/* Write the page contents to the target's page buffer. A page write
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* is issued automatically once the last location is written in the
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* page buffer (ie: a complete page has been written out). */
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res = target_write_memory(bank->target, address, 4,
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chip->page_size / 4, buf);
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if (res != ERROR_OK) {
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LOG_ERROR("%s: %d", __func__, __LINE__);
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return res;
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}
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/* For some devices automatic page write is not default so we need
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* to issue a write page CMD to the NVM */
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if (chip->manual_wp == true) {
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res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
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if (res != ERROR_OK) {
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LOG_ERROR("%s: %d", __func__, __LINE__);
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return res;
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}
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}
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/* Access through AHB is stalled while flash is being programmed */
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usleep(200);
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error = samd_check_error(bank->target);
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if (error)
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return ERROR_FAIL;
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/* Next page */
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address += chip->page_size;
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buf += chip->page_size;
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}
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sector->is_erased = 0;
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return res;
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}
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/* Write partial contents into row-aligned 'address' on the Flash from host
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* buffer 'buf' by writing 'nb' of 'buf' at 'row_offset' into the Flash row. */
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static int samd_write_row_partial(struct flash_bank *bank, uint32_t address,
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const uint8_t *buf, uint32_t row_offset, uint32_t nb)
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{
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int res;
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struct samd_info *chip = (struct samd_info *)bank->driver_priv;
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uint32_t row_size = chip->page_size * 4;
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uint8_t *rb = malloc(row_size);
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if (!rb)
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return ERROR_FAIL;
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assert(row_offset + nb < row_size);
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assert((address % row_size) == 0);
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/* Retrieve the full row contents from Flash */
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res = target_read_memory(bank->target, address, 4, row_size / 4, rb);
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if (res != ERROR_OK) {
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free(rb);
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return res;
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}
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/* Insert our partial row over the data from Flash */
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memcpy(rb + (row_offset % row_size), buf, nb);
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/* Write the row back out */
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res = samd_write_row(bank, address, rb);
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free(rb);
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return res;
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}
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static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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@ -804,13 +668,15 @@ static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
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int res;
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uint32_t nvm_ctrlb;
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uint32_t address;
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uint32_t nb = 0;
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uint32_t pg_offset;
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uint32_t nb;
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uint32_t nw;
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struct samd_info *chip = (struct samd_info *)bank->driver_priv;
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uint32_t row_size = chip->page_size * 4;
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uint8_t *pb = NULL;
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bool manual_wp;
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if (bank->target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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@ -826,66 +692,93 @@ static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
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return res;
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if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
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chip->manual_wp = true;
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manual_wp = true;
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else
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chip->manual_wp = false;
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manual_wp = false;
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if (offset % row_size) {
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/* We're starting at an unaligned offset so we'll write a partial row
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* comprising that offset and up to the end of that row. */
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nb = row_size - (offset % row_size);
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if (nb > count)
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nb = count;
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} else if (count < row_size) {
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/* We're writing an aligned but partial row. */
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nb = count;
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res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
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if (res != ERROR_OK) {
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LOG_ERROR("%s: %d", __func__, __LINE__);
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return res;
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}
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address = (offset / row_size) * row_size + bank->base;
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while (count) {
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nb = chip->page_size - offset % chip->page_size;
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if (count < nb)
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nb = count;
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if (nb > 0) {
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res = samd_write_row_partial(bank, address, buffer,
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offset % row_size, nb);
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if (res != ERROR_OK)
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return res;
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address = bank->base + offset;
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pg_offset = offset % chip->page_size;
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/* We're done with the row contents */
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if (offset % 4 || (offset + nb) % 4) {
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/* Either start or end of write is not word aligned */
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if (!pb) {
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pb = malloc(chip->page_size);
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if (!pb)
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return ERROR_FAIL;
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}
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/* Set temporary page buffer to 0xff and overwrite the relevant part */
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memset(pb, 0xff, chip->page_size);
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memcpy(pb + pg_offset, buffer, nb);
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/* Align start address to a word boundary */
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address -= offset % 4;
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pg_offset -= offset % 4;
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assert(pg_offset % 4 == 0);
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/* Extend length to whole words */
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nw = (nb + offset % 4 + 3) / 4;
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assert(pg_offset + 4 * nw <= chip->page_size);
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/* Now we have original data extended by 0xff bytes
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* to the nearest word boundary on both start and end */
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res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
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} else {
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assert(nb % 4 == 0);
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nw = nb / 4;
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assert(pg_offset + 4 * nw <= chip->page_size);
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/* Word aligned data, use direct write from buffer */
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res = target_write_memory(bank->target, address, 4, nw, buffer);
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}
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if (res != ERROR_OK) {
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LOG_ERROR("%s: %d", __func__, __LINE__);
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goto free_pb;
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}
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/* Devices with errata 13134 have automatic page write enabled by default
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* For other devices issue a write page CMD to the NVM
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* If the page has not been written up to the last word
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* then issue CMD_WP always */
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if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
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res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
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if (res != ERROR_OK) {
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LOG_ERROR("%s: %d", __func__, __LINE__);
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goto free_pb;
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}
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}
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/* Access through AHB is stalled while flash is being programmed */
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usleep(200);
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if (samd_check_error(bank->target)) {
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LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
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res = ERROR_FAIL;
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goto free_pb;
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}
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/* We're done with the page contents */
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count -= nb;
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offset += nb;
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buffer += row_size;
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buffer += nb;
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}
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/* There's at least one aligned row to write out. */
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if (count >= row_size) {
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int nr = count / row_size + ((count % row_size) ? 1 : 0);
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unsigned int r = 0;
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free_pb:
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if (pb)
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free(pb);
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for (unsigned int i = address / row_size;
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(i < (address / row_size) + nr) && count > 0; i++) {
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address = (i * row_size) + bank->base;
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if (count >= row_size) {
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res = samd_write_row(bank, address, buffer + (r * row_size));
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/* Advance one row */
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offset += row_size;
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count -= row_size;
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} else {
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res = samd_write_row_partial(bank, address,
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buffer + (r * row_size), 0, count);
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/* We're done after this. */
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offset += count;
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count = 0;
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}
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r++;
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if (res != ERROR_OK)
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return res;
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}
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}
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return ERROR_OK;
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}
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FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
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