ARM: memory utils aren't ARM7/ARM9 dependent
The arm7_9_checksum_memory() and arm7_9_blank_check_memory() routines are not actually specific to the ARM7 and ARM9 core generations ... they can work for any core which can run algorithms using basic ARM (not Thumb) instructions. Rename them; move the declarations to a more generic site; likewise move the code (and tidy it a bit in the process). NOTE: the blank_check() method falsely returned a success status (0) on one error path, when the algorithm failed. Fixed this bug. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>__archive__
David Brownell
parent
9ac7cdec82
commit
269040bbad
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@ -535,8 +535,9 @@ struct target_type arm720t_target =
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.virt2phys = arm720_virt2phys,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.checksum_memory = arm_checksum_memory,
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.blank_check_memory = arm_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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@ -2706,156 +2706,6 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
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return retval;
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}
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int arm7_9_checksum_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum)
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{
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struct working_area *crc_algorithm;
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struct armv4_5_algorithm armv4_5_info;
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struct reg_param reg_params[2];
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int retval;
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static const uint32_t arm7_9_crc_code[] = {
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0xE1A02000, /* mov r2, r0 */
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0xE3E00000, /* mov r0, #0xffffffff */
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0xE1A03001, /* mov r3, r1 */
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0xE3A04000, /* mov r4, #0 */
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0xEA00000B, /* b ncomp */
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/* nbyte: */
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0xE7D21004, /* ldrb r1, [r2, r4] */
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0xE59F7030, /* ldr r7, CRC32XOR */
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0xE0200C01, /* eor r0, r0, r1, asl 24 */
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0xE3A05000, /* mov r5, #0 */
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/* loop: */
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0xE3500000, /* cmp r0, #0 */
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0xE1A06080, /* mov r6, r0, asl #1 */
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0xE2855001, /* add r5, r5, #1 */
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0xE1A00006, /* mov r0, r6 */
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0xB0260007, /* eorlt r0, r6, r7 */
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0xE3550008, /* cmp r5, #8 */
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0x1AFFFFF8, /* bne loop */
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0xE2844001, /* add r4, r4, #1 */
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/* ncomp: */
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0xE1540003, /* cmp r4, r3 */
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0x1AFFFFF1, /* bne nbyte */
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/* end: */
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0xEAFFFFFE, /* b end */
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0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
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};
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uint32_t i;
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if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
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{
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* convert flash writing code into a buffer in target endianness */
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for (i = 0; i < (sizeof(arm7_9_crc_code)/sizeof(uint32_t)); i++)
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{
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if ((retval = target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), arm7_9_crc_code[i])) != ERROR_OK)
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{
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return retval;
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}
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}
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armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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buf_set_u32(reg_params[0].value, 0, 32, address);
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buf_set_u32(reg_params[1].value, 0, 32, count);
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/* 20 second timeout/megabyte */
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int timeout = 20000 * (1 + (count / (1024*1024)));
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if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
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crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), timeout, &armv4_5_info)) != ERROR_OK)
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{
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LOG_ERROR("error executing arm7_9 crc algorithm");
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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target_free_working_area(target, crc_algorithm);
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return retval;
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}
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*checksum = buf_get_u32(reg_params[0].value, 0, 32);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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target_free_working_area(target, crc_algorithm);
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return ERROR_OK;
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}
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int arm7_9_blank_check_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* blank)
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{
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struct working_area *erase_check_algorithm;
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struct reg_param reg_params[3];
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struct armv4_5_algorithm armv4_5_info;
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int retval;
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uint32_t i;
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static const uint32_t erase_check_code[] =
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{
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/* loop: */
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0xe4d03001, /* ldrb r3, [r0], #1 */
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0xe0022003, /* and r2, r2, r3 */
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0xe2511001, /* subs r1, r1, #1 */
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0x1afffffb, /* bne loop */
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/* end: */
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0xeafffffe /* b end */
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};
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/* make sure we have a working area */
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if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
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{
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* convert flash writing code into a buffer in target endianness */
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for (i = 0; i < (sizeof(erase_check_code)/sizeof(uint32_t)); i++)
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if ((retval = target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t), erase_check_code[i])) != ERROR_OK)
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{
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return retval;
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}
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armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
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buf_set_u32(reg_params[0].value, 0, 32, address);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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buf_set_u32(reg_params[1].value, 0, 32, count);
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init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
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buf_set_u32(reg_params[2].value, 0, 32, 0xff);
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if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
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erase_check_algorithm->address, erase_check_algorithm->address + (sizeof(erase_check_code) - 4), 10000, &armv4_5_info)) != ERROR_OK)
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{
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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target_free_working_area(target, erase_check_algorithm);
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return 0;
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}
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*blank = buf_get_u32(reg_params[2].value, 0, 32);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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target_free_working_area(target, erase_check_algorithm);
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return ERROR_OK;
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}
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/**
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* Perform per-target setup that requires JTAG access.
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*/
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@ -143,8 +143,6 @@ int arm7_9_read_core_reg(struct target *target, int num, enum armv4_5_mode mode)
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int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
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int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer);
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int arm7_9_checksum_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* checksum);
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int arm7_9_blank_check_memory(struct target *target, uint32_t address, uint32_t count, uint32_t* blank);
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int arm7_9_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_prams, struct reg_param *reg_param, uint32_t entry_point, void *arch_info);
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@ -737,8 +737,9 @@ struct target_type arm7tdmi_target =
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.read_memory = arm7_9_read_memory,
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.write_memory = arm7_9_write_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.checksum_memory = arm_checksum_memory,
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.blank_check_memory = arm_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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@ -1407,8 +1407,9 @@ struct target_type arm920t_target =
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.virt2phys = arm920_virt2phys,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.checksum_memory = arm_checksum_memory,
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.blank_check_memory = arm_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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@ -864,8 +864,9 @@ struct target_type arm926ejs_target =
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.read_memory = arm7_9_read_memory,
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.write_memory = arm926ejs_write_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.checksum_memory = arm_checksum_memory,
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.blank_check_memory = arm_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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@ -261,8 +261,9 @@ struct target_type arm966e_target =
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.read_memory = arm7_9_read_memory,
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.write_memory = arm7_9_write_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.checksum_memory = arm_checksum_memory,
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.blank_check_memory = arm_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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@ -938,8 +938,9 @@ struct target_type arm9tdmi_target =
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.read_memory = arm7_9_read_memory,
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.write_memory = arm7_9_write_memory,
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.bulk_write_memory = arm7_9_bulk_write_memory,
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.checksum_memory = arm7_9_checksum_memory,
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.blank_check_memory = arm7_9_blank_check_memory,
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.checksum_memory = arm_checksum_memory,
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.blank_check_memory = arm_blank_check_memory,
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.run_algorithm = armv4_5_run_algorithm,
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@ -707,6 +707,176 @@ int armv4_5_run_algorithm(struct target *target, int num_mem_params, struct mem_
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return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
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}
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/**
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* Runs ARM code in the target to calculate a CRC32 checksum.
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*
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* \todo On ARMv5+, rely on BKPT termination for reduced overhead.
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*/
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int arm_checksum_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t *checksum)
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{
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struct working_area *crc_algorithm;
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struct armv4_5_algorithm armv4_5_info;
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struct reg_param reg_params[2];
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int retval;
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uint32_t i;
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static const uint32_t arm_crc_code[] = {
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0xE1A02000, /* mov r2, r0 */
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0xE3E00000, /* mov r0, #0xffffffff */
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0xE1A03001, /* mov r3, r1 */
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0xE3A04000, /* mov r4, #0 */
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0xEA00000B, /* b ncomp */
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/* nbyte: */
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0xE7D21004, /* ldrb r1, [r2, r4] */
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0xE59F7030, /* ldr r7, CRC32XOR */
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0xE0200C01, /* eor r0, r0, r1, asl 24 */
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0xE3A05000, /* mov r5, #0 */
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/* loop: */
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0xE3500000, /* cmp r0, #0 */
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0xE1A06080, /* mov r6, r0, asl #1 */
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0xE2855001, /* add r5, r5, #1 */
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0xE1A00006, /* mov r0, r6 */
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0xB0260007, /* eorlt r0, r6, r7 */
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0xE3550008, /* cmp r5, #8 */
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0x1AFFFFF8, /* bne loop */
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0xE2844001, /* add r4, r4, #1 */
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/* ncomp: */
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0xE1540003, /* cmp r4, r3 */
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0x1AFFFFF1, /* bne nbyte */
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/* end: */
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0xEAFFFFFE, /* b end */
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/* CRC32XOR: */
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0x04C11DB7 /* .word 0x04C11DB7 */
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};
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retval = target_alloc_working_area(target,
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sizeof(arm_crc_code), &crc_algorithm);
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if (retval != ERROR_OK)
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return retval;
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/* convert code into a buffer in target endianness */
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for (i = 0; i < DIM(arm_crc_code); i++) {
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retval = target_write_u32(target,
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crc_algorithm->address + i * sizeof(uint32_t),
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arm_crc_code[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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buf_set_u32(reg_params[0].value, 0, 32, address);
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buf_set_u32(reg_params[1].value, 0, 32, count);
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/* 20 second timeout/megabyte */
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int timeout = 20000 * (1 + (count / (1024 * 1024)));
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retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
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crc_algorithm->address,
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crc_algorithm->address + sizeof(arm_crc_code) - 8,
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timeout, &armv4_5_info);
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if (retval != ERROR_OK) {
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LOG_ERROR("error executing ARM crc algorithm");
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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target_free_working_area(target, crc_algorithm);
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return retval;
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}
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*checksum = buf_get_u32(reg_params[0].value, 0, 32);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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target_free_working_area(target, crc_algorithm);
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return ERROR_OK;
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}
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/**
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* Runs ARM code in the target to check whether a memory block holds
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* all ones. NOR flash which has been erased, and thus may be written,
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* holds all ones.
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*
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* \todo On ARMv5+, rely on BKPT termination for reduced overhead.
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*/
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int arm_blank_check_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t *blank)
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{
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struct working_area *check_algorithm;
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struct reg_param reg_params[3];
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struct armv4_5_algorithm armv4_5_info;
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int retval;
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uint32_t i;
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static const uint32_t check_code[] = {
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/* loop: */
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0xe4d03001, /* ldrb r3, [r0], #1 */
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0xe0022003, /* and r2, r2, r3 */
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0xe2511001, /* subs r1, r1, #1 */
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0x1afffffb, /* bne loop */
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/* end: */
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0xeafffffe /* b end */
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};
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/* make sure we have a working area */
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retval = target_alloc_working_area(target,
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sizeof(check_code), &check_algorithm);
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if (retval != ERROR_OK)
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return retval;
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/* convert code into a buffer in target endianness */
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for (i = 0; i < DIM(check_code); i++) {
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retval = target_write_u32(target,
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check_algorithm->address
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+ i * sizeof(uint32_t),
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check_code[i]);
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if (retval != ERROR_OK)
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return retval;
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}
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armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
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armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
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armv4_5_info.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
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buf_set_u32(reg_params[0].value, 0, 32, address);
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
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buf_set_u32(reg_params[1].value, 0, 32, count);
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|
||||
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
|
||||
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
|
||||
|
||||
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
|
||||
check_algorithm->address,
|
||||
check_algorithm->address + sizeof(check_code) - 4,
|
||||
10000, &armv4_5_info);
|
||||
if (retval != ERROR_OK) {
|
||||
destroy_reg_param(®_params[0]);
|
||||
destroy_reg_param(®_params[1]);
|
||||
destroy_reg_param(®_params[2]);
|
||||
target_free_working_area(target, check_algorithm);
|
||||
return retval;
|
||||
}
|
||||
|
||||
*blank = buf_get_u32(reg_params[2].value, 0, 32);
|
||||
|
||||
destroy_reg_param(®_params[0]);
|
||||
destroy_reg_param(®_params[1]);
|
||||
destroy_reg_param(®_params[2]);
|
||||
|
||||
target_free_working_area(target, check_algorithm);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5)
|
||||
{
|
||||
target->arch_info = armv4_5;
|
||||
|
|
|
|||
|
|
@ -190,6 +190,12 @@ int armv4_5_run_algorithm(struct target *target,
|
|||
|
||||
int armv4_5_invalidate_core_regs(struct target *target);
|
||||
|
||||
int arm_checksum_memory(struct target *target,
|
||||
uint32_t address, uint32_t count, uint32_t *checksum);
|
||||
int arm_blank_check_memory(struct target *target,
|
||||
uint32_t address, uint32_t count, uint32_t *blank);
|
||||
|
||||
|
||||
/* ARM mode instructions
|
||||
*/
|
||||
|
||||
|
|
@ -369,7 +375,4 @@ static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_
|
|||
return t;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* ARMV4_5_H */
|
||||
|
|
|
|||
|
|
@ -1590,8 +1590,9 @@ struct target_type cortexa8_target = {
|
|||
.read_memory = cortex_a8_read_memory,
|
||||
.write_memory = cortex_a8_write_memory,
|
||||
.bulk_write_memory = cortex_a8_bulk_write_memory,
|
||||
.checksum_memory = arm7_9_checksum_memory,
|
||||
.blank_check_memory = arm7_9_blank_check_memory,
|
||||
|
||||
.checksum_memory = arm_checksum_memory,
|
||||
.blank_check_memory = arm_blank_check_memory,
|
||||
|
||||
.run_algorithm = armv4_5_run_algorithm,
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,6 @@
|
|||
#include "register.h"
|
||||
#include "target.h"
|
||||
#include "armv7a.h"
|
||||
#include "arm7_9_common.h"
|
||||
|
||||
extern char* cortex_a8_state_strings[];
|
||||
|
||||
|
|
|
|||
|
|
@ -380,8 +380,9 @@ struct target_type fa526_target =
|
|||
.read_memory = arm920t_read_memory,
|
||||
.write_memory = arm920t_write_memory,
|
||||
.bulk_write_memory = arm7_9_bulk_write_memory,
|
||||
.checksum_memory = arm7_9_checksum_memory,
|
||||
.blank_check_memory = arm7_9_blank_check_memory,
|
||||
|
||||
.checksum_memory = arm_checksum_memory,
|
||||
.blank_check_memory = arm_blank_check_memory,
|
||||
|
||||
.run_algorithm = armv4_5_run_algorithm,
|
||||
|
||||
|
|
|
|||
|
|
@ -696,8 +696,9 @@ struct target_type feroceon_target =
|
|||
.read_memory = arm7_9_read_memory,
|
||||
.write_memory = arm926ejs_write_memory,
|
||||
.bulk_write_memory = feroceon_bulk_write_memory,
|
||||
.checksum_memory = arm7_9_checksum_memory,
|
||||
.blank_check_memory = arm7_9_blank_check_memory,
|
||||
|
||||
.checksum_memory = arm_checksum_memory,
|
||||
.blank_check_memory = arm_blank_check_memory,
|
||||
|
||||
.run_algorithm = armv4_5_run_algorithm,
|
||||
|
||||
|
|
@ -734,8 +735,9 @@ struct target_type dragonite_target =
|
|||
.read_memory = arm7_9_read_memory,
|
||||
.write_memory = arm7_9_write_memory,
|
||||
.bulk_write_memory = feroceon_bulk_write_memory,
|
||||
.checksum_memory = arm7_9_checksum_memory,
|
||||
.blank_check_memory = arm7_9_blank_check_memory,
|
||||
|
||||
.checksum_memory = arm_checksum_memory,
|
||||
.blank_check_memory = arm_blank_check_memory,
|
||||
|
||||
.run_algorithm = armv4_5_run_algorithm,
|
||||
|
||||
|
|
|
|||
|
|
@ -3626,8 +3626,9 @@ struct target_type xscale_target =
|
|||
.read_memory = xscale_read_memory,
|
||||
.write_memory = xscale_write_memory,
|
||||
.bulk_write_memory = xscale_bulk_write_memory,
|
||||
.checksum_memory = arm7_9_checksum_memory,
|
||||
.blank_check_memory = arm7_9_blank_check_memory,
|
||||
|
||||
.checksum_memory = arm_checksum_memory,
|
||||
.blank_check_memory = arm_blank_check_memory,
|
||||
|
||||
.run_algorithm = armv4_5_run_algorithm,
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue