zcy
/
tinyriscv-openocd
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

update IXP42x target / XBA board config

__archive__
Michael Schwingen 2010-12-19 16:17:46 +01:00 committed by Øyvind Harboe
parent 6839618062
commit 23bf724e04
3 changed files with 130 additions and 96 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
tcl/board/actux3.cfg Normal file
View File

@ -0,0 +1,47 @@
# board config file for AcTux3/XBA IXP42x board
# Date: 2010-12-16
# Author: Michael Schwingen <michael@schwingen.org>
reset_config trst_and_srst separate
adapter_nsrst_delay 100
jtag_ntrst_delay 100
source [find target/ixp42x.cfg]
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
$_TARGETNAME configure -event reset-init { init_actux3 }
proc init_actux3 { } {
##########################################################################
# setup expansion bus CS
##########################################################################
mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
mww 0xc4000004 0x94d10013 ;#CS1
mww 0xc4000008 0x95960003 ;#CS2
mww 0xc400000c 0x00000000 ;#CS3
mww 0xc4000010 0x80900003 ;#CS4
mww 0xc4000014 0x9d520003 ;#CS5
mww 0xc4000018 0x81860001 ;#CS6
mww 0xc400001c 0x80900003 ;#CS7
ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
#mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
ixp42x_set_bigendian
flash probe 0
}
proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
echo "writing bootloader: $FILE"
flash write_image erase $FILE 0x50000000 bin
}
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
init
reset init

91
tcl/target/ixp42x.cfg
View File

@ -1,6 +1,5 @@
#xscale ixp42x CPU
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@ -17,16 +16,92 @@ if { [info exists ENDIAN] } {
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
# force an error till we get a good number
set _CPUTAPID 0xffffffff
set _CPUTAPID 0x19274013
}
set _CPUTAPID2 0x19275013
set _CPUTAPID3 0x19277013
set _CPUTAPID4 0x29274013
set _CPUTAPID5 0x29275013
set _CPUTAPID6 0x29277013
#use combined on interfaces or targets that can?t set TRST/SRST separately
reset_config srst_only srst_pulls_trst
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2 -expected-id $_CPUTAPID3 -expected-id $_CPUTAPID4 -expected-id $_CPUTAPID5 -expected-id $_CPUTAPID6
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
# register constants for IXP42x SDRAM controller
global IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
global IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
set IXP425_SDRAM_IR_MODE_SET_CAS2_CMD 0x0000
set IXP425_SDRAM_IR_MODE_SET_CAS3_CMD 0x0001
global IXP42x_SDRAM_CL3
global IXP42x_SDRAM_CL2
set IXP42x_SDRAM_CL3 0x0008
set IXP42x_SDRAM_CL2 0x0000
global IXP42x_SDRAM_8MB_2Mx32_1BANK
global IXP42x_SDRAM_16MB_2Mx32_2BANK
global IXP42x_SDRAM_16MB_4Mx16_1BANK
global IXP42x_SDRAM_32MB_4Mx16_2BANK
global IXP42x_SDRAM_32MB_8Mx16_1BANK
global IXP42x_SDRAM_64MB_8Mx16_2BANK
global IXP42x_SDRAM_64MB_16Mx16_1BANK
global IXP42x_SDRAM_128MB_16Mx16_2BANK
global IXP42x_SDRAM_128MB_32Mx16_1BANK
global IXP42x_SDRAM_256MB_32Mx16_2BANK
set IXP42x_SDRAM_8MB_2Mx32_1BANK 0x0030
set IXP42x_SDRAM_16MB_2Mx32_2BANK 0x0031
set IXP42x_SDRAM_16MB_4Mx16_1BANK 0x0032
set IXP42x_SDRAM_32MB_4Mx16_2BANK 0x0033
set IXP42x_SDRAM_32MB_8Mx16_1BANK 0x0010
set IXP42x_SDRAM_64MB_8Mx16_2BANK 0x0011
set IXP42x_SDRAM_64MB_16Mx16_1BANK 0x0012
set IXP42x_SDRAM_128MB_16Mx16_2BANK 0x0013
set IXP42x_SDRAM_128MB_32Mx16_1BANK 0x0014
set IXP42x_SDRAM_256MB_32Mx16_2BANK 0x0015
# helper function to init SDRAM on IXP42x.
# SDRAM_CFG: one of IXP42X_SDRAM_xxx
# REFRESH: refresh counter reload value (integer)
# CASLAT: 2 or 3
proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
switch $CASLAT {
2 {
set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL2 ]
set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS2_CMD
}
3 {
set SDRAM_CFG [expr $SDRAM_CFG | $::IXP42x_SDRAM_CL3 ]
set CASCMD $::IXP425_SDRAM_IR_MODE_SET_CAS3_CMD
}
default { error [format "unsupported cas latency \"%s\" " $CASLAT] }
}
echo [format "\tIXP42x SDRAM Config: 0x%x, Refresh %d " $SDRAM_CFG $REFRESH]
mww 0xCC000000 $SDRAM_CFG ;# SDRAM_CFG: 0x2A: 64MBit, CL3
mww 0xCC000004 0 ;# disable refresh
mww 0xCC000008 3 ;# NOP
sleep 100
mww 0xCC000004 $REFRESH ;# set refresh counter
mww 0xCC000008 2 ;# Precharge All Banks
sleep 100
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 $CASCMD ;# Mode Select CL2/CL3
}
proc ixp42x_set_bigendian { } {
reg XSCALE_CTRL 0xF8
}

88
tcl/target/xba_revA3.cfg
View File

@ -1,88 +0,0 @@
#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME xba_reva3
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
# default to big endian
set _ENDIAN big
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
# force an error till we get a good number
set _CPUTAPID 0xffffffff
}
reset_config trst_and_srst separate
adapter_nsrst_delay 100
jtag_ntrst_delay 100
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
$_TARGETNAME configure -event reset-init {
#############################################################################
# setup expansion bus CS, disable external wdt
#############################################################################
mww 0xc4000000 0xbd113842 ;#CS0 : Flash, write enabled @0x50000000
mww 0xc4000004 0x94d10013 ;#CS1
mww 0xc4000008 0x95960003 ;#CS2
mww 0xc400000c 0x00000000 ;#CS3
mww 0xc4000010 0x80900003 ;#CS4
mww 0xc4000014 0x9d520003 ;#CS5
mww 0xc4000018 0x81860001 ;#CS6
mww 0xc400001c 0x80900003 ;#CS7
#############################################################################
# init SDRAM controller: 16MB, one bank, CL3
#############################################################################
mww 0xCC000000 0x2A ;# SDRAM_CFG: 64MBit, CL3
mww 0xCC000004 0 ;# disable refresh
mww 0xCC000008 3 ;# NOP
sleep 100
mww 0xCC000004 2100 ;# set refresh counter
mww 0xCC000008 2 ;# Precharge All Banks
sleep 100
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 4 ;# Auto Refresh
mww 0xCC000008 1 ;# Mode Select CL3
#mww 0xc4000020 0xffffee ;# CFG0: remove expansion bus boot flash
#mirror at 0x00000000
#big endian
reg XSCALE_CTRL 0xF8
#
# detect flash
#
flash probe 0
}
$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
init
reset init
# set big endian mode
reg XSCALE_CTRL 0xF8