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arm_adi_v5: Split CSW bits into AHB/APB/AXI 

The implementation-defined bits have different semantics for each bus
and different recommended defaults.

Change-Id: I562fe24643bb1f3abc696339e382a75ccf2f2873
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-on: http://openocd.zylin.com/5124
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
bscan_optimization
Leonard Crestez 2019-04-16 22:12:18 +03:00 committed by Tomas Vanek
parent 51ef02a5d1
commit 2288394b45
3 changed files with 27 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/target/arm_adi_v5.c
View File

@ -1745,7 +1745,7 @@ COMMAND_HANDLER(dap_apcsw_command)
return ERROR_OK; return ERROR_OK;
case 1: case 1:
if (strcmp(CMD_ARGV[0], "default") == 0) if (strcmp(CMD_ARGV[0], "default") == 0)
csw_val = CSW_DEFAULT; csw_val = CSW_AHB_DEFAULT;
else else
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val); COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);

31
src/target/arm_adi_v5.h
View File

@ -112,15 +112,34 @@
#define CSW_ADDRINC_PACKED (2UL << 4) #define CSW_ADDRINC_PACKED (2UL << 4)
#define CSW_DEVICE_EN (1UL << 6) #define CSW_DEVICE_EN (1UL << 6)
#define CSW_TRIN_PROG (1UL << 7) #define CSW_TRIN_PROG (1UL << 7)
/* all fields in bits 12 and above are implementation-defined! */
/* All fields in bits 12 and above are implementation-defined
* Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
* Some bits are shared between buses
*/
#define CSW_SPIDEN (1UL << 23) #define CSW_SPIDEN (1UL << 23)
#define CSW_HPROT1 (1UL << 25) /* AHB: Privileged */
#define CSW_MASTER_DEBUG (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */
#define CSW_SPROT (1UL << 30)
#define CSW_DBGSWENABLE (1UL << 31) #define CSW_DBGSWENABLE (1UL << 31)
/* initial value of csw_default used for MEM-AP transfers */ /* AHB: Privileged */
#define CSW_DEFAULT (CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE) #define CSW_AHB_HPROT1 (1UL << 25)
/* AHB: set HMASTER signals to AHB-AP ID */
#define CSW_AHB_MASTER_DEBUG (1UL << 29)
/* AHB5: non-secure access via HNONSEC
* AHB3: SBO, UNPREDICTABLE if zero */
#define CSW_AHB_SPROT (1UL << 30)
/* AHB: initial value of csw_default */
#define CSW_AHB_DEFAULT (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
/* AXI: Privileged */
#define CSW_AXI_ARPROT0_PRIV (1UL << 28)
/* AXI: Non-secure */
#define CSW_AXI_ARPROT1_NONSEC (1UL << 29)
/* AXI: initial value of csw_default */
#define CSW_AXI_DEFAULT (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
/* APB: initial value of csw_default */
#define CSW_APB_DEFAULT (CSW_DBGSWENABLE)
/* Fields of the MEM-AP's IDR register */ /* Fields of the MEM-AP's IDR register */
#define IDR_REV (0xFUL << 28) #define IDR_REV (0xFUL << 28)

2
src/target/arm_dap.c
View File

@ -56,7 +56,7 @@ static void dap_instance_init(struct adiv5_dap *dap)
/* Number of bits for tar autoincrement, impl. dep. at least 10 */ /* Number of bits for tar autoincrement, impl. dep. at least 10 */
dap->ap[i].tar_autoincr_block = (1<<10); dap->ap[i].tar_autoincr_block = (1<<10);
/* default CSW value */ /* default CSW value */
dap->ap[i].csw_default = CSW_DEFAULT; dap->ap[i].csw_default = CSW_AHB_DEFAULT;
} }
INIT_LIST_HEAD(&dap->cmd_journal); INIT_LIST_HEAD(&dap->cmd_journal);
} }