Once more... Less sloppy this time.

Change-Id: I4a24e777af3a0d8e072bc1bce0b314738393aa86
2018-03-27 11:42:32 -07:00 · 2018-03-27 11:42:32 -07:00 · 224e7b4f16
parent 0c05aafbf8
commit 224e7b4f16
1 changed files with 1 additions and 1 deletions
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@ -2329,7 +2329,7 @@ int riscv_init_registers(struct target *target)
 					 * U-mode but without U-mode trap support, the medeleg and
 					 * mideleg registers should not exist." */
 					r->exist = riscv_supports_extension(target, 'S') ||
-						!riscv_supports_extension(target, 'N');
+						riscv_supports_extension(target, 'N');
 					break;
 			}