aarch64: formalize use of CTI in halt and resume
Use configured CTI base address instead of hardcoded value, if available. Use symbolic constants instead of raw hex offsets. Trim halt and resume code to what is actually necessary. Change-Id: I4997c2bcca7cebf5ad78859a6a12abe8639594ed Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>gitignore-build
Matthias Welwarsky
parent
4ba8388f26
commit
21a5c40430
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@ -796,59 +796,49 @@ static int aarch64_halt(struct target *target)
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uint32_t dscr;
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struct armv8_common *armv8 = target_to_armv8(target);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0, &dscr);
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/* enable CTI*/
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0, 1);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0, &dscr);
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armv8->cti_base + CTI_CTR, 1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x140, &dscr);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x140, 6);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x140, &dscr);
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armv8->cti_base + CTI_GATE, 3);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0xa0, &dscr);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0xa0, 5);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0xa0, &dscr);
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armv8->cti_base + CTI_OUTEN0, 1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0xa4, &dscr);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0xa4, 2);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0xa4, &dscr);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x20, &dscr);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x20, 4);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x20, &dscr);
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armv8->cti_base + CTI_OUTEN1, 2);
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if (retval != ERROR_OK)
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return retval;
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/*
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* enter halting debug mode
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* add HDE in halting debug mode
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*/
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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# /* STATUS */
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x134, &dscr);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x1c, &dscr);
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x1c, 1);
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x1c, &dscr);
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armv8->debug_base + CPUV8_DBG_DSCR, dscr | DSCR_HDE);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->cti_base + CTI_APPPULSE, 1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->cti_base + CTI_INACK, 1);
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if (retval != ERROR_OK)
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return retval;
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long long then = timeval_ms();
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@ -857,7 +847,7 @@ static int aarch64_halt(struct target *target)
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armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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if ((dscr & DSCR_CORE_HALTED) != 0)
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if ((dscr & DSCRV8_HALT_MASK) != 0)
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break;
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if (timeval_ms() > then + 1000) {
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LOG_ERROR("Timeout waiting for halt");
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@ -969,23 +959,7 @@ static int aarch64_internal_restart(struct target *target)
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LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_DSCR, dscr & ~DSCR_ITR_EN);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_DRCR, DRCR_RESTART |
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DRCR_CLEAR_EXCEPTIONS);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x10, 1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + 0x10000 + 0x1c, 2);
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armv8->cti_base + CTI_APPPULSE, 2);
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if (retval != ERROR_OK)
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return retval;
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@ -995,7 +969,7 @@ static int aarch64_internal_restart(struct target *target)
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armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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if ((dscr & DSCR_CORE_RESTARTED) != 0)
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if ((dscr & DSCR_HDE) != 0)
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break;
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if (timeval_ms() > then + 1000) {
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LOG_ERROR("Timeout waiting for resume");
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@ -1061,11 +1035,11 @@ static int aarch64_resume(struct target *target, int current,
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if (!debug_execution) {
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target->state = TARGET_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
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LOG_DEBUG("target resumed at 0x%" PRIu64, addr);
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LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
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} else {
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target->state = TARGET_DEBUG_RUNNING;
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target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
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LOG_DEBUG("target debug resumed at 0x%" PRIu64, addr);
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LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
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}
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return ERROR_OK;
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@ -2316,6 +2290,12 @@ static int aarch64_examine_first(struct target *target)
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} else
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armv8->debug_base = target->dbgbase;
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LOG_DEBUG("Target ctibase is 0x%x", target->ctibase);
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if (target->ctibase == 0)
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armv8->cti_base = target->ctibase = armv8->debug_base + 0x1000;
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else
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armv8->cti_base = target->ctibase;
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
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if (retval != ERROR_OK) {
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@ -130,6 +130,8 @@ struct armv8_common {
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/* Core Debug Unit */
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struct arm_dpm dpm;
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uint32_t debug_base;
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uint32_t cti_base;
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struct adiv5_ap *debug_ap;
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struct adiv5_ap *memory_ap;
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bool memory_ap_available;
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@ -191,6 +193,35 @@ target_to_armv8(struct target *target)
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#define CPUV8_DBG_AUTHSTATUS 0xFB8
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/*define CTI(cross trigger interface)*/
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#define CTI_CTR 0x0
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#define CTI_INACK 0x10
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#define CTI_APPSET 0x14
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#define CTI_APPCLEAR 0x18
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#define CTI_APPPULSE 0x1C
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#define CTI_INEN0 0x20
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#define CTI_INEN1 0x24
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#define CTI_INEN2 0x28
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#define CTI_INEN3 0x2C
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#define CTI_INEN4 0x30
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#define CTI_INEN5 0x34
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#define CTI_INEN6 0x38
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#define CTI_INEN7 0x3C
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#define CTI_OUTEN0 0xA0
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#define CTI_OUTEN1 0xA4
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#define CTI_OUTEN2 0xA8
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#define CTI_OUTEN3 0xAC
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#define CTI_OUTEN4 0xB0
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#define CTI_OUTEN5 0xB4
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#define CTI_OUTEN6 0xB8
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#define CTI_OUTEN7 0xBC
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#define CTI_TRIN_STATUS 0x130
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#define CTI_TROUT_STATUS 0x134
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#define CTI_CHIN_STATUS 0x138
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#define CTI_CHOU_STATUS 0x13C
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#define CTI_GATE 0x140
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#define CTI_UNLOCK 0xFB0
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int armv8_arch_state(struct target *target);
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int armv8_identify_cache(struct target *target);
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