Quickly read all GPRs on halt.
gdb will ask for them anyway, and one by one is slow. StepTest went from 9.7s to 5.3s.__archive__
Tim Newsome
parent
6fac5a41f8
commit
20e2bfe3db
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@ -24,6 +24,8 @@
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#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
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#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
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#define DIM(x) (sizeof(x)/sizeof(*x))
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#define CSR_TDRSELECT 0x7a0
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#define CSR_TDRDATA1 0x7a1
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#define CSR_TDRDATA2 0x7a2
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@ -71,6 +73,12 @@ typedef enum {
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#define DBUS_DATA_SIZE 34
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#define DBUS_ADDRESS_START 36
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typedef enum {
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RE_OK,
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RE_FAIL,
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RE_AGAIN
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} riscv_error_t;
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/*** Debug Bus registers. ***/
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#define DMCONTROL 0x10
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@ -151,13 +159,16 @@ typedef struct {
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// This value is incremented every time a dbus access comes back as "busy".
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// It's used to determine how many run-test/idle cycles to feed the target
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// in between accesses.
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unsigned int dbus_busy_count;
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unsigned int dbus_busy_delay;
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// This value is incremented every time we read the debug interrupt as
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// high. It's used to add extra run-test/idle cycles after setting debug
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// interrupt high, so ideally we never have to perform a whole extra scan
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// before the interrupt is cleared.
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unsigned int interrupt_high_count;
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unsigned int interrupt_high_delay;
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// This cache is write-through, and always valid when the target is halted.
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uint32_t gpr_cache[32];
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} riscv_info_t;
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typedef struct {
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@ -228,6 +239,47 @@ static int debug_scan(struct target *target)
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}
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#endif
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static void increase_dbus_busy_delay(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->dbus_busy_delay++;
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LOG_INFO("Increment dbus_busy_delay to %d", info->dbus_busy_delay);
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}
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static void increase_interrupt_high_delay(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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info->interrupt_high_delay++;
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LOG_INFO("Increment interrupt_high_delay to %d", info->interrupt_high_delay);
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}
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static void add_dbus_scan(struct target *target, struct scan_field *field,
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uint8_t *out_value, uint8_t *in_value, dbus_op_t op, uint16_t address,
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uint64_t data)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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LOG_DEBUG("op=%d address=0x%02x data=0x%09" PRIx64, op, address, data);
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field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
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field->in_value = in_value;
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field->out_value = out_value;
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buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
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buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
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buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
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jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
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// TODO: 1 should come from the dtminfo register
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int idle_count = 1 + info->dbus_busy_delay;
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if (data & DMCONTROL_INTERRUPT) {
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idle_count += info->interrupt_high_delay;
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}
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jtag_add_runtest(idle_count, TAP_IDLE);
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}
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static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
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uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
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{
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@ -477,28 +529,12 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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} else {
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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if (info->dram_cache[i].dirty) {
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field[scan].num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
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field[scan].out_value = out + 8*scan;
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field[scan].in_value = in + 8*scan;
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buf_set_u64(out + 8*scan, DBUS_OP_START, DBUS_OP_SIZE, DBUS_OP_WRITE);
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uint64_t data = DMCONTROL_HALTNOT | info->dram_cache[i].data;
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if (i == last && run) {
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buf_set_u64(out + 8*scan, DBUS_DATA_START, DBUS_DATA_SIZE,
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DMCONTROL_INTERRUPT | DMCONTROL_HALTNOT | info->dram_cache[i].data);
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} else {
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buf_set_u64(out + 8*scan, DBUS_DATA_START, DBUS_DATA_SIZE,
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DMCONTROL_HALTNOT | info->dram_cache[i].data);
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data |= DMCONTROL_INTERRUPT;
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}
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buf_set_u64(out + 8*scan, DBUS_ADDRESS_START, info->addrbits, i);
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jtag_add_dr_scan(target->tap, 1, &field[scan], TAP_IDLE);
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jtag_add_runtest(1 + info->dbus_busy_count, TAP_IDLE);
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LOG_DEBUG("write scan=%d result=%d data=%09" PRIx64 " address=%02x",
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scan,
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buf_get_u32(out + 8*scan, DBUS_OP_START, DBUS_OP_SIZE),
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buf_get_u64(out + 8*scan, DBUS_DATA_START, DBUS_DATA_SIZE),
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buf_get_u32(out + 8*scan, DBUS_ADDRESS_START, info->addrbits));
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_WRITE, i, data);
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scan++;
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}
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@ -507,34 +543,16 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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// Throw away the results of the first read, since it'll contain the result
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// of the read that happened just before debugint was set.
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field[scan].num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
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field[scan].out_value = out + 8*scan;
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field[scan].in_value = NULL;
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buf_set_u64(out + 8*scan, DBUS_OP_START, DBUS_OP_SIZE, DBUS_OP_READ);
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buf_set_u64(out + 8*scan, DBUS_DATA_START, DBUS_DATA_SIZE, DMCONTROL_HALTNOT | 0);
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buf_set_u64(out + 8*scan, DBUS_ADDRESS_START, info->addrbits, address);
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jtag_add_dr_scan(target->tap, 1, &field[scan], TAP_IDLE);
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jtag_add_runtest(1 + info->dbus_busy_count + info->interrupt_high_count, TAP_IDLE);
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add_dbus_scan(target, &field[scan], out + 8*scan, NULL, DBUS_OP_READ,
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address, DMCONTROL_HALTNOT);
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scan++;
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// This scan contains the results of the read the caller requested, as well
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// as an interrupt bit worth looking at.
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field[scan].num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
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field[scan].out_value = out + 8*scan;
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field[scan].in_value = in + 8*scan;
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buf_set_u64(out + 8*scan, DBUS_OP_START, DBUS_OP_SIZE, DBUS_OP_READ);
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buf_set_u64(out + 8*scan, DBUS_DATA_START, DBUS_DATA_SIZE, DMCONTROL_HALTNOT | 0);
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buf_set_u64(out + 8*scan, DBUS_ADDRESS_START, info->addrbits, address);
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jtag_add_dr_scan(target->tap, 1, &field[scan], TAP_IDLE);
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jtag_add_runtest(1 + info->dbus_busy_count, TAP_IDLE);
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan, DBUS_OP_READ,
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address, DMCONTROL_HALTNOT);
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scan++;
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("JTAG execute failed.");
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@ -565,8 +583,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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}
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if (errors) {
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LOG_INFO("Target couldn't handle our write speed. Slowing down...");
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info->dbus_busy_count++;
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increase_dbus_busy_delay(target);
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// Try again, using the slow careful code.
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for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
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@ -590,7 +607,7 @@ static int cache_write(struct target *target, unsigned int address, bool run)
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int interrupt = buf_get_u32(in + 8*(scan-1), DBUS_DATA_START + 33, 1);
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if (interrupt) {
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info->interrupt_high_count++;
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increase_interrupt_high_delay(target);
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// Slow path wait for it to clear.
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if (wait_for_debugint_clear(target, false) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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@ -783,6 +800,9 @@ static int resume(struct target *target, int current, uint32_t address,
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}
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target->state = TARGET_RUNNING;
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for (unsigned int i = 0; i < 32; i++) {
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info->gpr_cache[i] = 0xbadbad;
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}
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return ERROR_OK;
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}
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@ -814,21 +834,10 @@ static int register_get(struct reg *reg)
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struct target *target = (struct target *) reg->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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if (reg->number == S0) {
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cache_set(target, 0, csrr(S0, CSR_DSCRATCH));
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cache_set(target, 1, sw(S0, ZERO, DEBUG_RAM_START + 16));
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cache_set_jump(target, 2);
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} else if (reg->number == S1) {
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cache_set(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 4 * info->dramsize - 4));
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cache_set(target, 1, sw(S0, ZERO, DEBUG_RAM_START + 16));
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cache_set_jump(target, 2);
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} else if (reg->number == ZERO) {
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buf_set_u64(reg->value, 0, info->xlen, 0);
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LOG_DEBUG("%s=0x%x", reg->name, 0);
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if (reg->number <= REG_XPR31) {
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buf_set_u64(reg->value, 0, info->xlen, info->gpr_cache[reg->number]);
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LOG_DEBUG("%s=0x%x", reg->name, info->gpr_cache[reg->number]);
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return ERROR_OK;
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} else if (reg->number <= REG_XPR31) {
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cache_set(target, 0, sw(reg->number - REG_XPR0, ZERO, DEBUG_RAM_START + 16));
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cache_set_jump(target, 1);
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} else if (reg->number == REG_PC) {
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buf_set_u32(reg->value, 0, 32, info->dpc);
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LOG_DEBUG("%s=0x%x (cached)", reg->name, info->dpc);
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@ -850,6 +859,11 @@ static int register_get(struct reg *reg)
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}
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uint32_t value = cache_get32(target, 4);
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if (reg->number < 32 && info->gpr_cache[reg->number] != value) {
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LOG_ERROR("cached value for %s is 0x%x but just read 0x%x",
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reg->name, info->gpr_cache[reg->number], value);
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assert(info->gpr_cache[reg->number] == value);
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}
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uint32_t exception = cache_get32(target, info->dramsize-1);
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if (exception) {
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@ -906,10 +920,12 @@ static int register_write(struct target *target, unsigned int number,
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static int register_set(struct reg *reg, uint8_t *buf)
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{
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struct target *target = (struct target *) reg->arch_info;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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uint32_t value = buf_get_u32(buf, 0, 32);
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LOG_DEBUG("write 0x%x to %s", value, reg->name);
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info->gpr_cache[reg->number] = value;
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return register_write(target, reg->number, value);
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}
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@ -1210,18 +1226,202 @@ static int riscv_examine(struct target *target)
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return ERROR_OK;
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}
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static riscv_error_t handle_halt_routine(struct target *target)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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const unsigned int max_scan = 256;
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uint8_t *in = malloc(max_scan * 8);
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uint8_t *out = malloc(max_scan * 8);
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struct scan_field *field = calloc(max_scan, sizeof(struct scan_field));
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unsigned int scan = 0;
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// Read all GPRs as fast as we can, because gdb is going to ask for them
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// anyway. Reading them one at a time is much slower.
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// TODO
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// Write the jump back to address 1.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_WRITE, 1, DMCONTROL_HALTNOT |
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jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*1))));
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scan++;
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for (int reg = 1; reg < 32; reg++) {
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if (reg == S0 || reg == S1) {
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continue;
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}
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// Write store instruction.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_WRITE, 0, DMCONTROL_INTERRUPT | DMCONTROL_HALTNOT |
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sw(reg, ZERO, DEBUG_RAM_START + 16));
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scan++;
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// Read value.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_READ, 4, DMCONTROL_HALTNOT);
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scan++;
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assert(scan < max_scan);
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}
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// Write store of s0 at index 1.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_WRITE, 1, DMCONTROL_HALTNOT |
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sw(S0, ZERO, DEBUG_RAM_START + 16));
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scan++;
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// Write jump at index 2.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_WRITE, 2, DMCONTROL_HALTNOT |
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jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
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cache_set(target, 0, csrr(S0, CSR_DSCRATCH));
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scan++;
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// Read S1 from debug RAM
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_WRITE, 0, DMCONTROL_INTERRUPT | DMCONTROL_HALTNOT |
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lw(S0, ZERO, DEBUG_RAM_START + 4 * info->dramsize - 4));
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scan++;
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// Read value.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_READ, 4, DMCONTROL_HALTNOT);
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scan++;
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// Read S0 from dscratch
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unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
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for (unsigned int i = 0; i < DIM(csr); i++) {
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_WRITE, 0, DMCONTROL_INTERRUPT | DMCONTROL_HALTNOT |
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csrr(S0, csr[i]));
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scan++;
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// Read value.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_READ, 4, DMCONTROL_HALTNOT);
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scan++;
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assert(scan < max_scan);
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}
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// Final read to get the last value out.
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add_dbus_scan(target, &field[scan], out + 8*scan, in + 8*scan,
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DBUS_OP_READ, 4, DMCONTROL_HALTNOT);
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scan++;
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assert(scan < max_scan);
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int retval = jtag_execute_queue();
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if (retval != ERROR_OK) {
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LOG_ERROR("JTAG execute failed: %d", retval);
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goto error;
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}
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unsigned int dbus_busy = 0;
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unsigned int interrupt_set = 0;
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unsigned result = 0;
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info->gpr_cache[0] = 0;
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// The first scan result is the result from something old we don't care
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// about.
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for (unsigned int i = 1; i < scan && dbus_busy == 0; i++) {
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dbus_status_t status = buf_get_u32(in + 8*i, DBUS_OP_START, DBUS_OP_SIZE);
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uint64_t data = buf_get_u64(in + 8*i, DBUS_DATA_START, DBUS_DATA_SIZE);
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uint32_t address = buf_get_u32(in + 8*i, DBUS_ADDRESS_START, info->addrbits);
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LOG_DEBUG("read scan=%d result=%d data=%09" PRIx64 " address=%02x",
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i, status, data, address);
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switch (status) {
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case DBUS_STATUS_SUCCESS:
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break;
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case DBUS_STATUS_NO_WRITE:
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LOG_ERROR("Got no-write response without conditional write. Hardware error?");
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goto error;
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case DBUS_STATUS_FAILED:
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LOG_ERROR("Debug access failed. Hardware error?");
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goto error;
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case DBUS_STATUS_BUSY:
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dbus_busy++;
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break;
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}
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if (data & DMCONTROL_INTERRUPT) {
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interrupt_set++;
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break;
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}
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if (address == 4) {
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switch (result) {
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case 0: info->gpr_cache[1] = data; break;
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case 1: info->gpr_cache[2] = data; break;
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case 2: info->gpr_cache[3] = data; break;
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case 3: info->gpr_cache[4] = data; break;
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case 4: info->gpr_cache[5] = data; break;
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case 5: info->gpr_cache[6] = data; break;
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case 6: info->gpr_cache[7] = data; break;
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// S0
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// S1
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case 7: info->gpr_cache[10] = data; break;
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case 8: info->gpr_cache[11] = data; break;
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case 9: info->gpr_cache[12] = data; break;
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case 10: info->gpr_cache[13] = data; break;
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case 11: info->gpr_cache[14] = data; break;
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case 12: info->gpr_cache[15] = data; break;
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case 13: info->gpr_cache[16] = data; break;
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case 14: info->gpr_cache[17] = data; break;
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case 15: info->gpr_cache[18] = data; break;
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case 16: info->gpr_cache[19] = data; break;
|
||||
case 17: info->gpr_cache[20] = data; break;
|
||||
case 18: info->gpr_cache[21] = data; break;
|
||||
case 19: info->gpr_cache[22] = data; break;
|
||||
case 20: info->gpr_cache[23] = data; break;
|
||||
case 21: info->gpr_cache[24] = data; break;
|
||||
case 22: info->gpr_cache[25] = data; break;
|
||||
case 23: info->gpr_cache[26] = data; break;
|
||||
case 24: info->gpr_cache[27] = data; break;
|
||||
case 25: info->gpr_cache[28] = data; break;
|
||||
case 26: info->gpr_cache[29] = data; break;
|
||||
case 27: info->gpr_cache[30] = data; break;
|
||||
case 28: info->gpr_cache[31] = data; break;
|
||||
case 29: info->gpr_cache[S1] = data; break;
|
||||
case 30: info->gpr_cache[S0] = data; break;
|
||||
case 31: info->dpc = data; break;
|
||||
case 32: info->dcsr = data; break;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
result++;
|
||||
}
|
||||
}
|
||||
|
||||
free(in);
|
||||
free(out);
|
||||
free(field);
|
||||
|
||||
cache_invalidate(target);
|
||||
|
||||
if (dbus_busy) {
|
||||
increase_dbus_busy_delay(target);
|
||||
return RE_AGAIN;
|
||||
}
|
||||
if (interrupt_set) {
|
||||
increase_interrupt_high_delay(target);
|
||||
return RE_AGAIN;
|
||||
}
|
||||
|
||||
return RE_OK;
|
||||
|
||||
error:
|
||||
free(in);
|
||||
free(out);
|
||||
free(field);
|
||||
return RE_FAIL;
|
||||
}
|
||||
|
||||
static int handle_halt(struct target *target)
|
||||
{
|
||||
riscv_info_t *info = (riscv_info_t *) target->arch_info;
|
||||
target->state = TARGET_HALTED;
|
||||
|
||||
if (read_csr(target, &info->dpc, CSR_DPC) != ERROR_OK) {
|
||||
riscv_error_t re;
|
||||
do {
|
||||
re = handle_halt_routine(target);
|
||||
} while (re == RE_AGAIN);
|
||||
if (re != RE_OK) {
|
||||
LOG_ERROR("handle_halt_routine failed");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (read_csr(target, &info->dcsr, CSR_DCSR) != ERROR_OK) {
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
int cause = get_field(info->dcsr, DCSR_CAUSE);
|
||||
LOG_DEBUG("halt cause is %d; dcsr=0x%x", cause, info->dcsr);
|
||||
switch (cause) {
|
||||
|
|
@ -1440,33 +1640,6 @@ static int riscv_read_memory(struct target *target, uint32_t address,
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
static void add_dbus_scan(struct target *target, struct scan_field *field,
|
||||
uint8_t *out_value, uint8_t *in_value, dbus_op_t op, uint16_t address,
|
||||
uint64_t data)
|
||||
{
|
||||
riscv_info_t *info = (riscv_info_t *) target->arch_info;
|
||||
|
||||
LOG_DEBUG("op=%d address=0x%02x data=0x%09" PRIx64, op, address, data);
|
||||
|
||||
field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
|
||||
field->in_value = in_value;
|
||||
field->out_value = out_value;
|
||||
|
||||
buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
|
||||
buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
|
||||
buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
|
||||
|
||||
jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
|
||||
|
||||
// TODO: 1 should come from the dtminfo register
|
||||
int idle_count = 1 + info->dbus_busy_count;
|
||||
if (data & DMCONTROL_INTERRUPT) {
|
||||
idle_count += info->interrupt_high_count;
|
||||
}
|
||||
|
||||
jtag_add_runtest(idle_count, TAP_IDLE);
|
||||
}
|
||||
|
||||
#if 1
|
||||
static int setup_write_memory(struct target *target, uint32_t size)
|
||||
{
|
||||
|
|
@ -1515,14 +1688,14 @@ static int riscv_write_memory(struct target *target, uint32_t address,
|
|||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
#define MAX_BATCH_SIZE 256
|
||||
uint8_t *in = malloc(MAX_BATCH_SIZE * 8);
|
||||
uint8_t *out = malloc(MAX_BATCH_SIZE * 8);
|
||||
struct scan_field *field = calloc(MAX_BATCH_SIZE, sizeof(struct scan_field));
|
||||
const int max_batch_size = 256;
|
||||
uint8_t *in = malloc(max_batch_size * 8);
|
||||
uint8_t *out = malloc(max_batch_size * 8);
|
||||
struct scan_field *field = calloc(max_batch_size, sizeof(struct scan_field));
|
||||
|
||||
uint32_t i = 0;
|
||||
while (i < count + 1) {
|
||||
unsigned int batch_size = MIN(count + 1 - i, MAX_BATCH_SIZE);
|
||||
unsigned int batch_size = MIN(count + 1 - i, max_batch_size);
|
||||
|
||||
for (unsigned int j = 0; j < batch_size; j++) {
|
||||
if (i + j == count) {
|
||||
|
|
@ -1584,12 +1757,10 @@ static int riscv_write_memory(struct target *target, uint32_t address,
|
|||
LOG_DEBUG("j=%d data=%09" PRIx64, j, buf_get_u64(in + 8*j, DBUS_DATA_START, DBUS_DATA_SIZE));
|
||||
}
|
||||
if (dbus_busy) {
|
||||
info->dbus_busy_count++;
|
||||
LOG_INFO("Increment dbus_busy_count to %d", info->dbus_busy_count);
|
||||
increase_dbus_busy_delay(target);
|
||||
}
|
||||
if (execute_busy) {
|
||||
info->interrupt_high_count++;
|
||||
LOG_INFO("Increment interrupt_high_count to %d", info->interrupt_high_count);
|
||||
increase_interrupt_high_delay(target);
|
||||
}
|
||||
if (dbus_busy || execute_busy) {
|
||||
wait_for_debugint_clear(target, false);
|
||||
|
|
|
|||
Loading…
Reference in New Issue