cortex_a8: add mrc mcr interface.
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>__archive__
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afed39c0fe
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1ebdc24494
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@ -70,6 +70,11 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target,
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int cortex_a8_assert_reset(target_t *target);
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int cortex_a8_assert_reset(target_t *target);
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int cortex_a8_deassert_reset(target_t *target);
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int cortex_a8_deassert_reset(target_t *target);
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static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1,
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uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
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static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1,
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uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
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target_type_t cortexa8_target =
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target_type_t cortexa8_target =
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{
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{
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.name = "cortex_a8",
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.name = "cortex_a8",
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@ -106,6 +111,8 @@ target_type_t cortexa8_target =
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.target_create = cortex_a8_target_create,
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.target_create = cortex_a8_target_create,
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.init_target = cortex_a8_init_target,
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.init_target = cortex_a8_init_target,
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.examine = cortex_a8_examine,
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.examine = cortex_a8_examine,
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.mrc = cortex_a8_mrc,
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.mcr = cortex_a8_mcr,
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};
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};
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/*
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/*
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@ -275,6 +282,28 @@ int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
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return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
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return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
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}
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}
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static int cortex_a8_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
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{
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if (cpnum!=15)
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{
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return cortex_a8_read_cp15(target, op1, op2, CRn, CRm, value);
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}
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static int cortex_a8_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
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{
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if (cpnum!=15)
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{
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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return cortex_a8_write_cp15(target, op1, op2, CRn, CRm, value);
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}
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int cortex_a8_dap_read_coreregister_u32(target_t *target,
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int cortex_a8_dap_read_coreregister_u32(target_t *target,
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uint32_t *value, int regnum)
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uint32_t *value, int regnum)
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{
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{
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