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target/arm_adi_v5: fix sync CSW cache on apreg write 

Commit 0057c71ab6 updates the OpenOCD
cached values of CSW and TAR registers if these registers are modified
by an apreg command.
The condition to force the update of CSW cache is incorrect and it will
erase the default CSW value.
Moreover, calling mem_ap_setup_csw() does not honor the value requested
in the apreg command because such value is incorrectly bitwise or-ed
with csw_default.

Fix it by updating csw_value, instead of erasing csw_default, and writing
directly in CSW register the new value from the command line.

Change-Id: I40273cb64d22ccfb9b6d3499bd39b586eb60de38
Fixes: 0057c71ab6 ("target/arm_adi_v5: sync CSW and TAR cache on apreg write")
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4679
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
bscan_tunnel
Antonio Borneo 2018-09-21 15:52:02 +02:00 committed by Matthias Welwarsky
parent d0be1630dc
commit 1ba715422f
1 changed files with 4 additions and 2 deletions
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6
src/target/arm_adi_v5.c
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@ -1738,8 +1738,10 @@ COMMAND_HANDLER(dap_apreg_command)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], value);
switch (reg) {
case MEM_AP_REG_CSW:
ap->csw_default = 0; /* invalid, force write */
retval = mem_ap_setup_csw(ap, value);
ap->csw_value = 0; /* invalid, in case write fails */
retval = dap_queue_ap_write(ap, reg, value);
if (retval == ERROR_OK)
ap->csw_value = value;
break;
case MEM_AP_REG_TAR:
ap->tar_valid = false; /* invalid, force write */