WIP hackery.
Main thing I added is code to output "verilog" for every JTAG op we do, so we can run the same thing in simulation.__archive__
Tim Newsome
parent
f40862d87c
commit
1b349df638
106
src/jtag/core.c
106
src/jtag/core.c
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@ -836,7 +836,111 @@ int default_interface_jtag_execute_queue(void)
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return ERROR_FAIL;
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}
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return jtag->execute_queue();
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int result = jtag->execute_queue();
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struct jtag_command *cmd = jtag_command_queue;
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while (debug_level >= LOG_LVL_DEBUG && cmd) {
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switch (cmd->type) {
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case JTAG_SCAN:
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LOG_DEBUG("JTAG %s SCAN to %s",
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cmd->cmd.scan->ir_scan ? "IR" : "DR",
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tap_state_name(cmd->cmd.scan->end_state));
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for (int i = 0; i < cmd->cmd.scan->num_fields; i++) {
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struct scan_field *field = cmd->cmd.scan->fields + i;
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if (field->out_value) {
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char *str = buf_to_str(field->out_value, field->num_bits, 16);
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LOG_DEBUG(" %db out: %s", field->num_bits, str);
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free(str);
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}
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if (field->in_value) {
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char *str = buf_to_str(field->in_value, field->num_bits, 16);
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LOG_DEBUG(" %db in: %s", field->num_bits, str);
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free(str);
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}
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if (field->check_value) {
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char *str = buf_to_str(field->check_value, field->num_bits, 16);
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LOG_DEBUG(" %db check: %s", field->num_bits, str);
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free(str);
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}
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if (field->check_mask) {
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char *str = buf_to_str(field->check_mask, field->num_bits, 16);
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LOG_DEBUG(" %db mask: %s", field->num_bits, str);
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free(str);
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}
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}
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uint8_t *buf = NULL;
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int scan_bits = jtag_build_buffer(cmd->cmd.scan, &buf);
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char *str_out = buf_to_str(buf, scan_bits, 16);
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free(buf);
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LOG_DEBUG("vvv jtag_scan(%d, %d, %d'h%s, %d); // %s",
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cmd->cmd.scan->ir_scan,
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scan_bits,
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scan_bits, str_out,
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cmd->cmd.scan->end_state, tap_state_name(cmd->cmd.scan->end_state));
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free(str_out);
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struct scan_field *last_field = cmd->cmd.scan->fields + cmd->cmd.scan->num_fields - 1;
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if (last_field->in_value) {
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char *str_in = buf_to_str(last_field->in_value, last_field->num_bits, 16);
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LOG_DEBUG("vvv jtag_check_tdo(%d, %d'h%s);",
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last_field->num_bits,
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last_field->num_bits, str_in);
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free(str_in);
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}
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break;
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case JTAG_TLR_RESET:
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LOG_DEBUG("JTAG TLR RESET to %s",
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tap_state_name(cmd->cmd.statemove->end_state));
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LOG_DEBUG("vvv jtag_tlr_reset(%d); // %s",
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cmd->cmd.statemove->end_state,
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tap_state_name(cmd->cmd.statemove->end_state));
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break;
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case JTAG_RUNTEST:
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LOG_DEBUG("JTAG RUNTEST %d cycles to %s",
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cmd->cmd.runtest->num_cycles,
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tap_state_name(cmd->cmd.runtest->end_state));
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LOG_DEBUG("vvv jtag_runtest(%d, %d); // %s",
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cmd->cmd.runtest->num_cycles,
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cmd->cmd.runtest->end_state,
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tap_state_name(cmd->cmd.runtest->end_state));
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break;
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case JTAG_RESET:
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{
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const char *reset_str[3] = {
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"leave", "deassert", "assert"
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};
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LOG_DEBUG("JTAG RESET %s TRST, %s SRST",
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reset_str[cmd->cmd.reset->trst + 1],
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reset_str[cmd->cmd.reset->srst + 1]);
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LOG_DEBUG("vvv jtag_reset(%d, %d);",
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cmd->cmd.reset->trst, cmd->cmd.reset->srst);
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}
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break;
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case JTAG_PATHMOVE:
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LOG_DEBUG("JTAG PATHMOVE (TODO)");
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abort();
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break;
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case JTAG_SLEEP:
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LOG_DEBUG("JTAG SLEEP (TODO)");
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abort();
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break;
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case JTAG_STABLECLOCKS:
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LOG_DEBUG("JTAG STABLECLOCKS (TODO)");
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abort();
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break;
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case JTAG_TMS:
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LOG_DEBUG("JTAG STABLECLOCKS (TODO)");
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abort();
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break;
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default:
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LOG_ERROR("Unknown JTAG command: %d", cmd->type);
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abort();
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break;
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}
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cmd = cmd->next;
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}
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return result;
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}
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void jtag_execute_queue_noclear(void)
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@ -79,22 +79,6 @@ static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
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MATCH_LB;
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}
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static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
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{
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return (bits(imm, 11, 0) << 20) |
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(src << 15) |
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(dest << 7) |
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MATCH_XORI;
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}
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static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
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{
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return (bits(shamt, 4, 0) << 20) |
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(src << 15) |
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(dest << 7) |
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MATCH_SRLI;
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}
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static uint32_t csrci(unsigned int csr, uint16_t imm) {
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return (csr << 20) |
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(bits(imm, 4, 0) << 15) |
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@ -126,7 +110,15 @@ static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
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MATCH_FSW;
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}
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/*
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static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
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{
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return (bits(offset, 11, 5) << 25) |
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(bits(src, 4, 0) << 20) |
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(base << 15) |
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(bits(offset, 4, 0) << 7) |
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MATCH_FLW;
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}
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static uint32_t li(unsigned int dest, uint16_t imm)
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{
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return addi(dest, 0, imm);
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@ -139,6 +131,7 @@ static uint32_t lui(unsigned int dest, uint32_t imm)
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MATCH_LUI;
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}
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/*
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static uint32_t fence_i(void)
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{
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return MATCH_FENCE_I;
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@ -186,8 +179,24 @@ static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
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(dest << 7) |
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MATCH_ORI;
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}
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static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
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{
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return (bits(imm, 11, 0) << 20) |
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(src << 15) |
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(dest << 7) |
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MATCH_XORI;
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}
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*/
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static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
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{
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return (bits(shamt, 4, 0) << 20) |
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(src << 15) |
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(dest << 7) |
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MATCH_SRLI;
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}
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static uint32_t nop(void)
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{
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return addi(0, 0, 0);
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@ -268,17 +268,21 @@ static uint32_t dram_read32(struct target *target, unsigned int index)
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static void dram_write32(struct target *target, unsigned int index, uint32_t value,
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bool set_interrupt)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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// TODO: check cache to see if this even needs doing.
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uint64_t dbus_value = DMCONTROL_HALTNOT | value;
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if (set_interrupt)
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dbus_value |= DMCONTROL_INTERRUPT;
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dbus_write(target, dram_address(index), dbus_value);
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info->dram_valid |= (1<<index);
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}
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#if 0
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static int dram_check32(struct target *target, unsigned int index,
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uint32_t expected)
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{
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uint32_t actual = dram_read32(target, index);
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uint16_t address = dram_address(index);
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uint32_t actual = dbus_read(target, address, address + 1);
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if (expected != actual) {
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LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
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expected, index, actual);
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@ -286,6 +290,7 @@ static int dram_check32(struct target *target, unsigned int index,
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}
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return ERROR_OK;
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}
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#endif
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/* Read the haltnot and interrupt bits. */
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static bits_t read_bits(struct target *target)
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@ -300,8 +305,14 @@ static bits_t read_bits(struct target *target)
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value = dbus_read(target, 0, next_address);
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}
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// Cycle through addresses, so we have more debug info.
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next_address = (next_address + 1) % 8;
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if (info->dram_valid) {
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// Cycle through addresses, so we have more debug info. Only look at
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// ones that we've written, to reduce data mismatch between real life
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// and simulation.
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do {
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next_address = (next_address + 1) % 64;
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} while (!(info->dram_valid & (1<<next_address)));
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}
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bits_t result = {
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.haltnot = get_field(value, DMCONTROL_HALTNOT),
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@ -416,6 +427,7 @@ static int register_get(struct reg *reg)
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{
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struct target *target = (struct target *) reg->arch_info;
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// TODO: S0 and S1
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if (reg->number <= REG_XPR31) {
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dram_write32(target, 0, sw(reg->number - REG_XPR0, ZERO, DEBUG_RAM_START), false);
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dram_write_jump(target, 1, true);
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@ -449,9 +461,42 @@ static int register_get(struct reg *reg)
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static int register_set(struct reg *reg, uint8_t *buf)
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{
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struct target *target = (struct target *) reg->arch_info;
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uint32_t value = buf_get_u32(buf, 0, 32);
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LOG_DEBUG("write 0x%x to %s", value, reg->name);
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// TODO: S0 and S1
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if (reg->number <= REG_XPR31) {
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dram_write32(target, 0, lw(reg->number - REG_XPR0, ZERO, DEBUG_RAM_START + 16), false);
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dram_write_jump(target, 1, false);
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} else if (reg->number == REG_PC) {
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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dram_write32(target, 1, csrw(S0, CSR_DPC), false);
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dram_write_jump(target, 2, false);
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} else if (reg->number >= REG_FPR0 && reg->number <= REG_FPR31) {
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dram_write32(target, 0, flw(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16), false);
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dram_write_jump(target, 1, false);
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} else if (reg->number >= REG_CSR0 && reg->number <= REG_CSR4095) {
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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dram_write32(target, 1, csrw(S0, reg->number - REG_CSR0), false);
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dram_write_jump(target, 2, false);
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} else {
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LOG_ERROR("Don't know how to read register %d (%s)", reg->number, reg->name);
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return ERROR_FAIL;
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}
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dram_write32(target, 4, value, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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static struct reg_arch_type riscv_reg_arch_type = {
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.get = register_get,
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.set = register_set
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@ -504,6 +549,8 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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}
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update_reg_list(target);
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info->dram_valid = 0;
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return ERROR_OK;
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}
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@ -649,7 +696,6 @@ static int riscv_examine(struct target *target)
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info->dram = malloc(info->dramsize * 4);
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if (!info->dram)
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return ERROR_FAIL;
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info->dram_valid = 0;
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if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
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LOG_ERROR("Authentication required by RISC-V core but not "
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@ -657,6 +703,7 @@ static int riscv_examine(struct target *target)
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return ERROR_FAIL;
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}
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#if 0
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// Figure out XLEN.
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dram_write32(target, 0, xori(S1, ZERO, -1), false);
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// 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff
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@ -691,7 +738,62 @@ static int riscv_examine(struct target *target)
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#else
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#if 1
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// Blue blue red
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dram_write32(target, 1, nop(), false);
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 0, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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#if 0
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// no effect
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dram_write32(target, 1, ~nop(), false);
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 0, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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srli(0,0,0);nop(); // TODO
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#if 0
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// Blue blue red red
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dram_write32(target, 0, nop(), false);
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dram_write32(target, 1, nop(), false);
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dram_write32(target, 2, sw(S1, ZERO, DEBUG_RAM_START), false);
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dram_write32(target, 3, srli(S1, S1, 31), false);
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 5, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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#if 0
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// Blue off red red
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dram_write32(target, 0, nop(), false);
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dram_write32(target, 1, sw(S1, ZERO, DEBUG_RAM_START), false);
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dram_write32(target, 2, srli(S1, S1, 31), false);
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dram_write32(target, 3, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 4, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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#endif
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#if 0
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uint32_t word0 = dram_read32(target, 0);
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uint32_t word1 = dram_read32(target, 1);
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if (word0 == 1 && word1 == 0) {
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@ -706,10 +808,38 @@ static int riscv_examine(struct target *target)
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return ERROR_FAIL;
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}
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LOG_DEBUG("Discovered XLEN is %d", info->xlen);
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#else
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info->xlen = 32;
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#endif
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// Update register list to match discovered XLEN.
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update_reg_list(target);
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// TODO
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// smoke test
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//dram_write32(target, 4, 0x700020a0, false);
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//dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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//dram_write32(target, 1, sw(ZERO, S0, 0), false);
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//dram_write32(target, 2, jal(ZERO, 0), true);
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//dram_write_jump(target, 2, true);
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li(0,0); // TODO: remove
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dram_write32(target, 0, lui(S0, 0x70002), false);
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dram_write32(target, 1, lui(S1, 0xccccc), false);
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dram_write32(target, 2, sw(S1, S0, 0xa0), false);
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dram_write32(target, 3, jal(ZERO, 0), true);
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// 400: 70002437 lui s0,0x70002
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// 404: 0a000493 li s1,160
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// 408: 0a942023 sw s1,160(s0) # 700020a0 <debug_ram+0x70001ca0>
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// 40c: 0000006f j 40c <debug_ram+0xc>
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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dram_read32(target, 4);
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target_set_examined(target);
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return ERROR_OK;
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@ -722,12 +852,16 @@ static int riscv_poll(struct target *target)
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if (bits.haltnot && bits.interrupt) {
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target->state = TARGET_DEBUG_RUNNING;
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LOG_DEBUG("debug running");
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} else if (bits.haltnot && !bits.interrupt) {
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target->state = TARGET_HALTED;
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LOG_DEBUG("halted");
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} else if (!bits.haltnot && bits.interrupt) {
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// Target is halting. There is no state for that, so don't change anything.
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LOG_DEBUG("halting");
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||||
} else if (!bits.haltnot && !bits.interrupt) {
|
||||
target->state = TARGET_RUNNING;
|
||||
LOG_DEBUG("running");
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
@ -866,6 +1000,7 @@ static int riscv_read_memory(struct target *target, uint32_t address,
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
#if 0
|
||||
static int riscv_write_memory(struct target *target, uint32_t address,
|
||||
uint32_t size, uint32_t count, const uint8_t *buffer)
|
||||
{
|
||||
|
|
@ -942,6 +1077,71 @@ static int riscv_write_memory(struct target *target, uint32_t address,
|
|||
|
||||
return ERROR_OK;
|
||||
}
|
||||
#else
|
||||
/** Inefficient implementation that doesn't require conditional writes. */
|
||||
static int riscv_write_memory(struct target *target, uint32_t address,
|
||||
uint32_t size, uint32_t count, const uint8_t *buffer)
|
||||
{
|
||||
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
|
||||
// TODO: save/restore T0
|
||||
|
||||
// Set up the address.
|
||||
|
||||
// Write program.
|
||||
dram_write32(target, 0, lw(S1, ZERO, DEBUG_RAM_START + 16), false);
|
||||
switch (size) {
|
||||
case 1:
|
||||
dram_write32(target, 1, lb(S0, ZERO, DEBUG_RAM_START + 20), false);
|
||||
dram_write32(target, 2, sb(S0, S1, 0), false);
|
||||
break;
|
||||
case 2:
|
||||
dram_write32(target, 1, lh(S0, ZERO, DEBUG_RAM_START + 20), false);
|
||||
dram_write32(target, 2, sh(S0, S1, 0), false);
|
||||
break;
|
||||
case 4:
|
||||
dram_write32(target, 1, lw(S0, ZERO, DEBUG_RAM_START + 20), false);
|
||||
dram_write32(target, 2, sw(S0, S1, 0), false);
|
||||
break;
|
||||
default:
|
||||
LOG_ERROR("Unsupported size: %d", size);
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
dram_write_jump(target, 3, false);
|
||||
|
||||
for (uint32_t i = 0; i < count; i++) {
|
||||
// Write the next value and set interrupt.
|
||||
uint32_t value;
|
||||
uint32_t offset = size * i;
|
||||
switch (size) {
|
||||
case 1:
|
||||
value = buffer[offset];
|
||||
break;
|
||||
case 2:
|
||||
value = buffer[offset] |
|
||||
(buffer[offset+1] << 8);
|
||||
break;
|
||||
case 4:
|
||||
value = buffer[offset] |
|
||||
((uint32_t) buffer[offset+1] << 8) |
|
||||
((uint32_t) buffer[offset+2] << 16) |
|
||||
((uint32_t) buffer[offset+3] << 24);
|
||||
break;
|
||||
default:
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
dram_write32(target, 4, address + offset, false);
|
||||
dram_write32(target, 5, value, true);
|
||||
|
||||
if (wait_for_debugint_clear(target) != ERROR_OK) {
|
||||
LOG_ERROR("Debug interrupt didn't clear.");
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int riscv_get_gdb_reg_list(struct target *target,
|
||||
struct reg **reg_list[], int *reg_list_size,
|
||||
|
|
|
|||
Loading…
Reference in New Issue