Nicolas Pitre nico at cam.org support for NAND flash used with Marvell Orion and Kirkwood SOCs
git-svn-id: svn://svn.berlios.de/openocd/trunk@1388 b42882b7-edfa-0310-969c-e2dbd0fdcd60__archive__
oharboe
parent
10edfff05a
commit
19ce96746d
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@ -3,7 +3,7 @@ AM_CPPFLAGS = -DPKGLIBDIR=\"$(pkglibdir)\" @CPPFLAGS@
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METASOURCES = AUTO
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noinst_LIBRARIES = libflash.a
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libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c at91sam7_old.c str7x.c str9x.c aduc702x.c nand.c lpc3180_nand_controller.c \
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stellaris.c str9xpec.c stm32x.c tms470.c ecos.c \
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stellaris.c str9xpec.c stm32x.c tms470.c ecos.c orion_nand.c \
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s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c pic32mx.c
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noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h at91sam7_old.h str7x.h str9x.h nand.h lpc3180_nand_controller.h \
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stellaris.h str9xpec.h stm32x.h tms470.h s3c24xx_nand.h s3c24xx_regs_nand.h lpc288x.h mflash.h \
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@ -61,6 +61,7 @@ int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_s
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/* NAND flash controller
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*/
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extern nand_flash_controller_t lpc3180_nand_controller;
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extern nand_flash_controller_t orion_nand_controller;
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extern nand_flash_controller_t s3c2410_nand_controller;
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extern nand_flash_controller_t s3c2412_nand_controller;
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extern nand_flash_controller_t s3c2440_nand_controller;
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@ -71,6 +72,7 @@ extern nand_flash_controller_t s3c2443_nand_controller;
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nand_flash_controller_t *nand_flash_controllers[] =
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{
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&lpc3180_nand_controller,
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&orion_nand_controller,
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&s3c2410_nand_controller,
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&s3c2412_nand_controller,
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&s3c2440_nand_controller,
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@ -0,0 +1,256 @@
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/***************************************************************************
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* Copyright (C) 2009 by Marvell Semiconductors, Inc. *
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* Written by Nicolas Pitre <nico at marvell.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/*
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* NAND controller interface for Marvell Orion/Kirkwood SoCs.
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "replacements.h"
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#include "log.h"
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#include <stdlib.h>
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#include <string.h>
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#include "nand.h"
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#include "target.h"
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#include "armv4_5.h"
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#include "binarybuffer.h"
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typedef struct orion_nand_controller_s
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{
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struct target_s *target;
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working_area_t *copy_area;
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u32 cmd;
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u32 addr;
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u32 data;
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} orion_nand_controller_t;
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#define CHECK_HALTED \
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do { \
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if (target->state != TARGET_HALTED) { \
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LOG_ERROR("NAND flash access requires halted target"); \
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return ERROR_NAND_OPERATION_FAILED; \
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} \
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} while (0)
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int orion_nand_command(struct nand_device_s *device, u8 command)
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{
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orion_nand_controller_t *hw = device->controller_priv;
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target_t *target = hw->target;
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CHECK_HALTED;
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target_write_u8(target, hw->cmd, command);
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return ERROR_OK;
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}
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int orion_nand_address(struct nand_device_s *device, u8 address)
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{
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orion_nand_controller_t *hw = device->controller_priv;
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target_t *target = hw->target;
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CHECK_HALTED;
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target_write_u8(target, hw->addr, address);
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return ERROR_OK;
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}
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int orion_nand_read(struct nand_device_s *device, void *data)
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{
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orion_nand_controller_t *hw = device->controller_priv;
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target_t *target = hw->target;
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CHECK_HALTED;
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target_read_u8(target, hw->data, data);
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return ERROR_OK;
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}
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int orion_nand_write(struct nand_device_s *device, u16 data)
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{
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orion_nand_controller_t *hw = device->controller_priv;
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target_t *target = hw->target;
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CHECK_HALTED;
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target_write_u8(target, hw->data, data);
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return ERROR_OK;
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}
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int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
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{
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while (size--)
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orion_nand_write(device, *data++);
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return ERROR_OK;
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}
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int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
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{
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orion_nand_controller_t *hw = device->controller_priv;
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target_t *target = hw->target;
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armv4_5_algorithm_t algo;
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reg_param_t reg_params[3];
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u32 target_buf;
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int retval;
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static const u32 code[] = {
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0xe4d13001, /* ldrb r3, [r1], #1 */
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0xe5c03000, /* strb r3, [r0] */
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0xe2522001, /* subs r2, r2, #1 */
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0x1afffffb, /* bne 0 */
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0xeafffffe, /* b . */
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};
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int code_size = sizeof(code);
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if (!hw->copy_area) {
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u8 code_buf[code_size];
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int i;
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/* make sure we have a working area */
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if (target_alloc_working_area(target,
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code_size + device->page_size,
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&hw->copy_area) != ERROR_OK)
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{
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return orion_nand_slow_block_write(device, data, size);
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}
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/* copy target instructions to target endianness */
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for (i = 0; i < code_size/4; i++)
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target_buffer_set_u32(target, code_buf + i*4, code[i]);
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/* write code to working area */
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retval = target->type->write_memory(target,
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hw->copy_area->address,
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4, code_size/4, code_buf);
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if (retval != ERROR_OK)
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return retval;
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}
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/* copy data to target's memory */
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target_buf = hw->copy_area->address + code_size;
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retval = target->type->bulk_write_memory(target, target_buf,
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size/4, data);
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if (retval == ERROR_OK && size & 3) {
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retval = target->type->write_memory(target,
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target_buf + (size & ~3),
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1, size & 3, data + (size & ~3));
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}
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if (retval != ERROR_OK)
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return retval;
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algo.common_magic = ARMV4_5_COMMON_MAGIC;
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algo.core_mode = ARMV4_5_MODE_SVC;
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algo.core_state = ARMV4_5_STATE_ARM;
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init_reg_param(®_params[0], "r0", 32, PARAM_IN);
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init_reg_param(®_params[1], "r1", 32, PARAM_IN);
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init_reg_param(®_params[2], "r2", 32, PARAM_IN);
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buf_set_u32(reg_params[0].value, 0, 32, hw->data);
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buf_set_u32(reg_params[1].value, 0, 32, target_buf);
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buf_set_u32(reg_params[2].value, 0, 32, size);
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retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
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hw->copy_area->address,
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hw->copy_area->address + code_size - 4,
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1000, &algo);
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if (retval != ERROR_OK)
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LOG_ERROR("error executing hosted NAND write");
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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return retval;
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}
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int orion_nand_reset(struct nand_device_s *device)
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{
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return orion_nand_command(device, NAND_CMD_RESET);
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}
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int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
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{
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return 1;
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}
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int orion_nand_register_commands(struct command_context_s *cmd_ctx)
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{
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return ERROR_OK;
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}
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int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
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char **args, int argc,
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struct nand_device_s *device)
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{
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orion_nand_controller_t *hw;
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u32 base;
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u8 ale, cle;
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if (argc != 3) {
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LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
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return ERROR_NAND_DEVICE_INVALID;
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}
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hw = calloc(1, sizeof(*hw));
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if (!hw) {
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LOG_ERROR("no memory for nand controller\n");
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return ERROR_NAND_DEVICE_INVALID;
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}
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device->controller_priv = hw;
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hw->target = get_target_by_num(strtoul(args[1], NULL, 0));
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if (!hw->target) {
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LOG_ERROR("no target '%s' configured", args[1]);
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free(hw);
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return ERROR_NAND_DEVICE_INVALID;
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}
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base = strtoul(args[2], NULL, 0);
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cle = 0;
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ale = 1;
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hw->data = base;
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hw->cmd = base + (1 << cle);
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hw->addr = base + (1 << ale);
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return ERROR_OK;
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}
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int orion_nand_init(struct nand_device_s *device)
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{
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return ERROR_OK;
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}
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nand_flash_controller_t orion_nand_controller =
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{
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.name = "orion",
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.command = orion_nand_command,
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.address = orion_nand_address,
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.read_data = orion_nand_read,
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.write_data = orion_nand_write,
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.write_block_data = orion_nand_fast_block_write,
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.reset = orion_nand_reset,
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.controller_ready = orion_nand_controller_ready,
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.nand_device_command = orion_nand_device_command,
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.register_commands = orion_nand_register_commands,
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.init = orion_nand_init,
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};
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