ARM: rename "arm9tdmi vector_catch" to "arm9 ..."
And update doc accordingly. That EmbeddedICE register was introduced for ARM9TDMI and then carried forward into most new chips that use EmbeddedICE.__archive__
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2
NEWS
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NEWS
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@ -19,6 +19,8 @@ Target Layer:
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VERY EARLY Cortex-A8 and ARMv7A support
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Updated BeagleBoard.org hardware support
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New commands for use with XScale processors: "xscale vector_table"
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ARM9
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name change: "arm9 vector_catch" not "arm9tdmi vector_catch"
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ARM11
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single stepping support for i.MX31
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bugfix for missing "arm11" prefix on "arm11 memwrite ..."
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TODO
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TODO
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@ -138,8 +138,7 @@ Once the above are completed:
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- regression: "reset halt" between 729(works) and 788(fails): @par
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https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
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- ARM7/9:
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- clean up "arm9tdmi vector_catch". Should be available for other arm9
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(e.g. arm926ejs) and some(???) arm7 cores. @par
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- clean up "arm9tdmi vector_catch". Available for some arm7 cores? @par
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https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html
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https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
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- add reset option to allow programming embedded ice while srst is asserted.
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@ -768,7 +768,7 @@ early boot code, which performs some of the same actions
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that the @code{reset-init} event handler does.
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@item
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Likewise, the @command{arm9tdmi vector_catch} command (or
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Likewise, the @command{arm9 vector_catch} command (or
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@cindex vector_catch
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its siblings @command{xscale vector_catch}
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and @command{cortex_m3 vector_catch}) can be a timesaver
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@ -5028,7 +5028,7 @@ at @var{address} for @var{length} bytes.
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This is a software breakpoint, unless @option{hw} is specified
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in which case it will be a hardware breakpoint.
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(@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
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(@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
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for similar mechanisms that do not consume hardware breakpoints.)
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@end deffn
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@ -5453,18 +5453,13 @@ ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
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integer processors.
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Such cores include the ARM920T, ARM926EJ-S, and ARM966.
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For historical reasons, one command shared by these cores starts
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with the @command{arm9tdmi} prefix.
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This is true even for ARM9E based processors, which implement the
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ARMv5TE architecture instead of ARMv4T.
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@c 9-june-2009: tried this on arm920t, it didn't work.
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@c no-params always lists nothing caught, and that's how it acts.
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@c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
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@c versions have different rules about when they commit writes.
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@anchor{arm9tdmi vector_catch}
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@deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
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@anchor{arm9 vector_catch}
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@deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
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@cindex vector_catch
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Vector Catch hardware provides a sort of dedicated breakpoint
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for hardware events such as reset, interrupt, and abort.
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@ -1061,14 +1061,12 @@ int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
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command_t *arm9tdmi_cmd;
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retval = arm7_9_register_commands(cmd_ctx);
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arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi",
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arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9",
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NULL, COMMAND_ANY,
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"arm9tdmi specific commands");
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"arm9 specific commands");
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register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
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handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
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"arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] - separate vectors to catch by space");
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"arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] ...");
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return retval;
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}
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