lpc2000: Add LPC407x/8x flash size auto detection
This patch adds auto flash size detection for LPC407x/8x series. Tested on below listed chips. LPC4088 LPC1788(regression test) Change-Id: I82f62678a04eac9b84658bd6d1cfdf45be64c931 Signed-off-by: Nemui Trinomius <nemuisan_kawausogasuki@live.jp> Reviewed-on: http://openocd.zylin.com/2555 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Jens Bauer <jens@gpio.dk>__archive__
Nemui Trinomius
Paul Fertser
parent
17bcbdaef1
commit
199acf668e
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@ -5208,7 +5208,7 @@ supported.}
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@deffn {Flash Driver} lpc2000
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This is the driver to support internal flash of all members of the
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LPC11(x)00 and LPC1300 microcontroller families and most members of
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the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4300 and LPC54100
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the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100
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microcontroller families from NXP.
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@quotation Note
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@ -5225,15 +5225,16 @@ which must appear in the following order:
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@item @var{variant} ... required, may be
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@option{lpc2000_v1} (older LPC21xx and LPC22xx)
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@option{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
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@option{lpc1700} (LPC175x and LPC176x)
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@option{lpc1700} (LPC175x and LPC176x and LPC177x/8x)
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@option{lpc4300} - available also as @option{lpc1800} alias (LPC18x[2357] and
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LPC43x[2357])
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@option{lpc800} (LPC8xx)
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@option{lpc1100} (LPC11(x)xx and LPC13xx)
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@option{lpc1500} (LPC15xx)
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@option{lpc54100} (LPC541xx)
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@option{lpc4000} (LPC40xx)
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or @option{auto} - automatically detects flash variant and size for LPC11(x)00,
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LPC8xx, LPC13xx and LPC17xx
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LPC8xx, LPC13xx, LPC17xx and LPC40xx
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@item @var{clock_kHz} ... the frequency, in kiloHertz,
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at which the core is running
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@item @option{calc_checksum} ... optional (but you probably want to provide this!),
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@ -40,7 +40,7 @@
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/**
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* @file
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* flash programming support for NXP LPC8xx,LPC1xxx,LPC43xx,LP5410x and LPC2xxx devices.
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* flash programming support for NXP LPC8xx,LPC1xxx,LPC4xxx,LP5410x and LPC2xxx devices.
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*
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* @todo Provide a way to update CCLK after declaring the flash bank. The value which is correct after chip reset will
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* rarely still work right after the clocks switch to use the PLL (e.g. 4MHz --> 100 MHz).
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@ -65,13 +65,20 @@
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* lpc1700:
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* - 175x
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* - 176x (tested with LPC1768)
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* - 177x
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* - 178x (tested with LPC1788)
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*
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* lpc4300 (also available as lpc1800 - alias)
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* lpc4000: (lpc1700's alias)
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* - 407x
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* - 408x (tested with LPC4088)
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*
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* lpc4300: (also available as lpc1800 - alias)
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* - 43x2 | 3 | 5 | 7 (tested with LPC4337/LPC4357)
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* - 18x2 | 3 | 5 | 7
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*
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* lpc800:
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* - 810 | 1 | 2 (tested with LPC810/LPC811/LPC812)
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* - 822 | 4 (tested with LPC824)
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*
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* lpc1100:
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* - 11xx
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@ -100,6 +107,10 @@
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* - 134x
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* - 175x
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* - 176x
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* - 177x
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* - 178x
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* - 407x
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* - 408x
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* - 81x
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* - 82x
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*/
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@ -229,6 +240,12 @@
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#define LPC1787 0x281D3747
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#define LPC1788 0x281D3F47
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#define LPC4072 0x47011121
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#define LPC4074 0x47011132
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#define LPC4076 0x47191F43
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#define LPC4078 0x47193F47
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#define LPC4088 0x481D3F47
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#define LPC810_021 0x00008100
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#define LPC811_001 0x00008110
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#define LPC812_101 0x00008120
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@ -467,7 +484,7 @@ static int lpc2000_build_sector_list(struct flash_bank *bank)
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for (int i = 0; i < bank->num_sectors; i++) {
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bank->sectors[i].offset = offset;
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/* sectors 0-15 are 4kB-sized, 16 and above are 32kB-sized for LPC17xx devices */
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/* sectors 0-15 are 4kB-sized, 16 and above are 32kB-sized for LPC17xx/LPC40xx devices */
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bank->sectors[i].size = (i < 16) ? 4 * 1024 : 32 * 1024;
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offset += bank->sectors[i].size;
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bank->sectors[i].is_erased = -1;
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@ -897,7 +914,7 @@ FLASH_BANK_COMMAND_HANDLER(lpc2000_flash_bank_command)
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lpc2000_info->variant = lpc2000_v1;
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} else if (strcmp(CMD_ARGV[6], "lpc2000_v2") == 0) {
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lpc2000_info->variant = lpc2000_v2;
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} else if (strcmp(CMD_ARGV[6], "lpc1700") == 0) {
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} else if (strcmp(CMD_ARGV[6], "lpc1700") == 0 || strcmp(CMD_ARGV[6], "lpc4000") == 0) {
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lpc2000_info->variant = lpc1700;
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} else if (strcmp(CMD_ARGV[6], "lpc1800") == 0 || strcmp(CMD_ARGV[6], "lpc4300") == 0) {
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lpc2000_info->variant = lpc4300;
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@ -1369,6 +1386,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
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break;
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case LPC1752:
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case LPC4072:
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lpc2000_info->variant = lpc1700;
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bank->size = 64 * 1024;
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break;
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@ -1395,6 +1413,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
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case LPC1754:
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case LPC1764:
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case LPC1774:
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case LPC4074:
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lpc2000_info->variant = lpc1700;
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bank->size = 128 * 1024;
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break;
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@ -1412,6 +1431,7 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
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case LPC1776:
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case LPC1785:
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case LPC1786:
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case LPC4076:
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lpc2000_info->variant = lpc1700;
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bank->size = 256 * 1024;
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break;
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@ -1425,6 +1445,8 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank)
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case LPC1778:
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case LPC1787:
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case LPC1788:
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case LPC4078:
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case LPC4088:
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lpc2000_info->variant = lpc1700;
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bank->size = 512 * 1024;
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break;
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@ -1,4 +1,4 @@
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# Main file for NXP LPC1xxx series Cortex-M0/0+/3 parts
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# Main file for NXP LPC1xxx/LPC40xx series Cortex-M0/0+/3/4F parts
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#
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# !!!!!!
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#
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@ -11,9 +11,10 @@
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# LPC8xx chips support only SWD transport.
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# LPC11xx chips support only SWD transport.
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# LPC12xx chips support only SWD transport.
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# LPC11Uxx chips support both JTAG and SWD transports.
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# LPC13xx chips support both JTAG and SWD transports.
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# LPC11Uxx chips support only SWD transports.
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# LPC13xx chips support only SWD transports.
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# LPC17xx chips support both JTAG and SWD transports.
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# LPC40xx chips support both JTAG and SWD transports.
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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@ -25,7 +26,7 @@ if { [info exists CHIPNAME] } {
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if { [info exists CHIPSERIES] } {
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# Validate chip series is supported
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if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" } {
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if { $CHIPSERIES != "lpc800" && $CHIPSERIES != "lpc1100" && $CHIPSERIES != "lpc1200" && $CHIPSERIES != "lpc1300" && $CHIPSERIES != "lpc1700" && $CHIPSERIES != "lpc4000" } {
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error "Unsupported LPC1xxx chip series specified."
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}
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set _CHIPSERIES $CHIPSERIES
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@ -43,10 +44,10 @@ if { [info exists CCLK] } {
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# Allow user override
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set _CCLK $CCLK
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} else {
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# LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one
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# LPC8xx/LPC11xx/LPC12xx/LPC13xx use a 12MHz one, LPC17xx uses a 4MHz one(except for LPC177x/8x,LPC407x/8x)
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if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" || $_CHIPSERIES == "lpc1300" } {
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set _CCLK 12000
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} elseif { $_CHIPSERIES == "lpc1700" } {
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} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
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set _CCLK 4000
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}
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}
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@ -55,10 +56,10 @@ if { [info exists CPUTAPID] } {
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# Allow user override
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set _CPUTAPID $CPUTAPID
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} else {
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# LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core
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# LPC8xx/LPC11xx/LPC12xx use a Cortex M0/M0+ core, LPC13xx/LPC17xx use a Cortex M3 core,LPC40xx use a Cortex-M4F core.
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if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "lpc1200" } {
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set _CPUTAPID 0x0bb11477
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} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" } {
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} elseif { $_CHIPSERIES == "lpc1300" || $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
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if { [using_jtag] } {
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set _CPUTAPID 0x4ba00477
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} {
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@ -82,7 +83,8 @@ target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
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# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC11Uxx devices have 4/6/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC13xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC17xx devices have 8/16/32kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC17xx devices have 8/16/32/64kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
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# The LPC40xx devices have 16/32/64kB of SRAM in the ARMv7-ME "Code" area (at 0x10000000)
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
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# The LPC11xx devies have 8/16/24/32/48/56/64kB of flash memory (at 0x00000000)
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@ -90,6 +92,7 @@ $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE
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# The LPC11Uxx devies have 16/24/32/40/48/64/96/128kB of flash memory (at 0x00000000)
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# The LPC13xx devies have 8/16/32kB of flash memory (at 0x00000000)
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# The LPC17xx devies have 32/64/128/256/512kB of flash memory (at 0x00000000)
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# The LPC40xx devies have 64/128/256/512kB of flash memory (at 0x00000000)
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#
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# All are compatible with the "lpc1700" variant of the LPC2000 flash driver
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# (same cmd51 destination boundary alignment, and all three support 256 byte
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@ -115,7 +118,7 @@ if { $_CHIPSERIES == "lpc800" || $_CHIPSERIES == "lpc1100" || $_CHIPSERIES == "l
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$_TARGETNAME configure -event reset-init {
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mww 0x40048000 0x02
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}
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} elseif { $_CHIPSERIES == "lpc1700" } {
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} elseif { $_CHIPSERIES == "lpc1700" || $_CHIPSERIES == "lpc4000" } {
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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@ -148,6 +151,7 @@ if {[using_jtag]} {
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# LPC8xx (Cortex M0+ core) support SYSRESETREQ
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# LPC11xx/LPC12xx (Cortex M0 core) support SYSRESETREQ
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# LPC13xx/LPC17xx (Cortex M3 core) support SYSRESETREQ
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# LPC40xx (Cortex M4F core) support SYSRESETREQ
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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@ -0,0 +1,8 @@
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# NXP LPC40xx Cortex-M4F with at least 16kB SRAM
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set CHIPNAME lpc40xx
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set CHIPSERIES lpc4000
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if { ![info exists WORKAREASIZE] } {
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set WORKAREASIZE 0x4000
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}
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source [find target/lpc1xxx.cfg]
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