aarch64: remove code for AHB-AP support
Reduce complexity of memory access functions, anyway there are no ARMv8 platforms that actually contain an AHB-AP at all. while at it, fix virt-to-phys function signatures to expect target_addr_t. Change-Id: I55a369686f42993988b6323e5a77f38de12530a9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>gitignore-build
Matthias Welwarsky
parent
9cc8cfe1b8
commit
1826f0af1c
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@ -2113,26 +2113,16 @@ static int aarch64_read_phys_memory(struct target *target,
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target_addr_t address, uint32_t size,
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uint32_t count, uint8_t *buffer)
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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int retval = ERROR_COMMAND_SYNTAX_ERROR;
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struct adiv5_dap *swjdp = armv8->arm.dap;
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uint8_t apsel = swjdp->apsel;
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LOG_DEBUG("Reading memory at real address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32,
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address, size, count);
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if (count && buffer) {
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if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
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/* read memory through AHB-AP */
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retval = mem_ap_read_buf(armv8->memory_ap, buffer, size, count, address);
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} else {
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/* read memory through APB-AP */
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retval = aarch64_mmu_modify(target, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = aarch64_read_apb_ap_memory(target, address, size, count, buffer);
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}
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/* read memory through APB-AP */
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retval = aarch64_mmu_modify(target, 0);
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if (retval != ERROR_OK)
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return retval;
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retval = aarch64_read_apb_ap_memory(target, address, size, count, buffer);
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}
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return retval;
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}
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@ -2141,11 +2131,7 @@ static int aarch64_read_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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int mmu_enabled = 0;
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target_addr_t virt, phys;
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int retval;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct adiv5_dap *swjdp = armv8->arm.dap;
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uint8_t apsel = swjdp->apsel;
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/* aarch64 handles unaligned memory access */
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LOG_DEBUG("Reading memory at address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32, address,
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@ -2156,116 +2142,33 @@ static int aarch64_read_memory(struct target *target, target_addr_t address,
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if (retval != ERROR_OK)
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return retval;
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if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
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if (mmu_enabled) {
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virt = address;
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retval = aarch64_virt2phys(target, virt, &phys);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("Reading at virtual address. Translating v:0x%" TARGET_PRIxADDR " to r:0x%" TARGET_PRIxADDR,
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virt, phys);
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address = phys;
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}
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retval = aarch64_read_phys_memory(target, address, size, count,
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buffer);
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} else {
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if (mmu_enabled) {
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retval = aarch64_check_address(target, address);
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if (retval != ERROR_OK)
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return retval;
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/* enable MMU as we could have disabled it for phys
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access */
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retval = aarch64_mmu_modify(target, 1);
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if (retval != ERROR_OK)
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return retval;
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}
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retval = aarch64_read_apb_ap_memory(target, address, size,
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count, buffer);
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if (mmu_enabled) {
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retval = aarch64_check_address(target, address);
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if (retval != ERROR_OK)
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return retval;
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/* enable MMU as we could have disabled it for phys access */
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retval = aarch64_mmu_modify(target, 1);
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if (retval != ERROR_OK)
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return retval;
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}
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return retval;
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return aarch64_read_apb_ap_memory(target, address, size, count, buffer);
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}
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static int aarch64_write_phys_memory(struct target *target,
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target_addr_t address, uint32_t size,
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uint32_t count, const uint8_t *buffer)
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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struct adiv5_dap *swjdp = armv8->arm.dap;
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int retval = ERROR_COMMAND_SYNTAX_ERROR;
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uint8_t apsel = swjdp->apsel;
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LOG_DEBUG("Writing memory to real address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32, address,
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size, count);
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if (count && buffer) {
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if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
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/* write memory through AHB-AP */
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retval = mem_ap_write_buf(armv8->memory_ap, buffer, size, count, address);
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} else {
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/* write memory through APB-AP */
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retval = aarch64_mmu_modify(target, 0);
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if (retval != ERROR_OK)
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return retval;
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return aarch64_write_apb_ap_memory(target, address, size, count, buffer);
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}
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}
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/* REVISIT this op is generic ARMv7-A/R stuff */
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if (retval == ERROR_OK && target->state == TARGET_HALTED) {
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struct arm_dpm *dpm = armv8->arm.dpm;
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retval = dpm->prepare(dpm);
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/* write memory through APB-AP */
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retval = aarch64_mmu_modify(target, 0);
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if (retval != ERROR_OK)
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return retval;
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/* The Cache handling will NOT work with MMU active, the
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* wrong addresses will be invalidated!
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*
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* For both ICache and DCache, walk all cache lines in the
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* address range. Cortex-A has fixed 64 byte line length.
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*
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* REVISIT per ARMv7, these may trigger watchpoints ...
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*/
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/* invalidate I-Cache */
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if (armv8->armv8_mmu.armv8_cache.i_cache_enabled) {
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/* ICIMVAU - Invalidate Cache single entry
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* with MVA to PoU
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* MCR p15, 0, r0, c7, c5, 1
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*/
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for (uint32_t cacheline = 0;
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cacheline < size * count;
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cacheline += 64) {
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retval = dpm->instr_write_data_r0(dpm,
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ARMV8_MSR_GP(SYSTEM_ICIVAU, 0),
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address + cacheline);
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if (retval != ERROR_OK)
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return retval;
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}
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}
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/* invalidate D-Cache */
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if (armv8->armv8_mmu.armv8_cache.d_u_cache_enabled) {
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/* DCIMVAC - Invalidate data Cache line
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* with MVA to PoC
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* MCR p15, 0, r0, c7, c6, 1
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*/
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for (uint32_t cacheline = 0;
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cacheline < size * count;
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cacheline += 64) {
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retval = dpm->instr_write_data_r0(dpm,
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ARMV8_MSR_GP(SYSTEM_DCCVAU, 0),
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address + cacheline);
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if (retval != ERROR_OK)
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return retval;
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}
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}
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/* (void) */ dpm->finish(dpm);
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return aarch64_write_apb_ap_memory(target, address, size, count, buffer);
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}
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return retval;
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@ -2275,11 +2178,7 @@ static int aarch64_write_memory(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer)
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{
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int mmu_enabled = 0;
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target_addr_t virt, phys;
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int retval;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct adiv5_dap *swjdp = armv8->arm.dap;
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uint8_t apsel = swjdp->apsel;
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/* aarch64 handles unaligned memory access */
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LOG_DEBUG("Writing memory at address 0x%" TARGET_PRIxADDR "; size %" PRId32
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@ -2290,34 +2189,16 @@ static int aarch64_write_memory(struct target *target, target_addr_t address,
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if (retval != ERROR_OK)
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return retval;
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if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
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LOG_DEBUG("Writing memory to address 0x%" TARGET_PRIxADDR "; size %"
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PRId32 "; count %" PRId32, address, size, count);
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if (mmu_enabled) {
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virt = address;
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retval = aarch64_virt2phys(target, virt, &phys);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("Writing to virtual address. Translating v:0x%"
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TARGET_PRIxADDR " to r:0x%" TARGET_PRIxADDR, virt, phys);
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address = phys;
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}
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retval = aarch64_write_phys_memory(target, address, size,
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count, buffer);
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} else {
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if (mmu_enabled) {
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retval = aarch64_check_address(target, address);
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if (retval != ERROR_OK)
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return retval;
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/* enable MMU as we could have disabled it for phys access */
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retval = aarch64_mmu_modify(target, 1);
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if (retval != ERROR_OK)
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return retval;
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}
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retval = aarch64_write_apb_ap_memory(target, address, size, count, buffer);
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if (mmu_enabled) {
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retval = aarch64_check_address(target, address);
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if (retval != ERROR_OK)
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return retval;
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/* enable MMU as we could have disabled it for phys access */
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retval = aarch64_mmu_modify(target, 1);
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if (retval != ERROR_OK)
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return retval;
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}
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return retval;
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return aarch64_write_apb_ap_memory(target, address, size, count, buffer);
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}
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static int aarch64_handle_target_request(void *priv)
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@ -2386,20 +2267,6 @@ static int aarch64_examine_first(struct target *target)
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armv8->debug_ap->memaccess_tck = 80;
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/* Search for the AHB-AB */
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armv8->memory_ap_available = false;
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retval = dap_find_ap(swjdp, AP_TYPE_AHB_AP, &armv8->memory_ap);
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if (retval == ERROR_OK) {
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retval = mem_ap_init(armv8->memory_ap);
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if (retval == ERROR_OK)
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armv8->memory_ap_available = true;
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}
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if (retval != ERROR_OK) {
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/* AHB-AP not found or unavailable - use the CPU */
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LOG_DEBUG("No AHB-AP available for memory access");
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}
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if (!target->dbgbase_set) {
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uint32_t dbgbase;
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/* Get ROM Table base */
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@ -2590,22 +2457,7 @@ static int aarch64_mmu(struct target *target, int *enabled)
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static int aarch64_virt2phys(struct target *target, target_addr_t virt,
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target_addr_t *phys)
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{
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int retval = ERROR_FAIL;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct adiv5_dap *swjdp = armv8->arm.dap;
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uint8_t apsel = swjdp->apsel;
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if (armv8->memory_ap_available && (apsel == armv8->memory_ap->ap_num)) {
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uint32_t ret;
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retval = armv8_mmu_translate_va(target,
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virt, &ret);
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if (retval != ERROR_OK)
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goto done;
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*phys = ret;
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} else {
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LOG_ERROR("AAR64 processor not support translate va to pa");
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}
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done:
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return retval;
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return armv8_mmu_translate_va(target, virt, phys);
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}
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COMMAND_HANDLER(aarch64_handle_cache_info_command)
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@ -382,7 +382,7 @@ done:
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return retval;
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}
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static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t *val)
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static int armv8_4K_translate(struct target *target, target_addr_t va, target_addr_t *val)
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{
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LOG_ERROR("4K page Address translation need to add");
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return ERROR_FAIL;
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@ -390,7 +390,7 @@ static int armv8_4K_translate(struct target *target, uint32_t va, uint32_t *val
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/* method adapted to cortex A : reused arm v4 v5 method*/
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int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val)
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int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val)
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{
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int retval = ERROR_FAIL;
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struct armv8_common *armv8 = target_to_armv8(target);
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@ -131,10 +131,8 @@ struct armv8_common {
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struct arm_dpm dpm;
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uint32_t debug_base;
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uint32_t cti_base;
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struct adiv5_ap *debug_ap;
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struct adiv5_ap *memory_ap;
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bool memory_ap_available;
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/* mdir */
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uint8_t multi_processor_system;
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uint8_t cluster_id;
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@ -245,7 +243,7 @@ int armv8_identify_cache(struct target *target);
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int armv8_init_arch_info(struct target *target, struct armv8_common *armv8);
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int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
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target_addr_t *val, int meminfo);
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int armv8_mmu_translate_va(struct target *target, uint32_t va, uint32_t *val);
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int armv8_mmu_translate_va(struct target *target, target_addr_t va, target_addr_t *val);
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int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache);
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