Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:
Some cleanup of the ARMv7-M support:
- Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
update the Cortex-M3 doc refs (DDI 0337C is no longer available).
- Those registers aren't actually general, and some are incorrect (per all
public docs anyway). Update comments and code accordingly.
* What the Core Debug facility exposes is *implementation-specific*
not architectural. These values aren't fully portable. They match
Cortex-M3 ... so no current implementation will make trouble, but
the next v7m implementation might.
* Four of the registers are actually not exposed that way. Before
Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
In that newest silicon, they are four bytes in one register, not
four separate registers.
- Update the CM3 code to report when that one register is available,
and not try to access it when it isn't. Also declare the register
numbers that an eventual MRS/MSR solution will need to be using.
- Stop line wrapping the exception labels.
So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.
Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts. Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
__archive__
zwelch
parent
0c2ff267aa
commit
16e17ab1b3
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@ -25,6 +25,10 @@
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* ARMv7-M Architecture, Application Level Reference Manual *
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* ARM DDI 0405C (September 2008) *
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* *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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@ -44,8 +48,10 @@ char* armv7m_mode_strings[] =
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char* armv7m_exception_strings[] =
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{
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"", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED",
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"SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick"
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"", "Reset", "NMI", "HardFault",
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"MemManage", "BusFault", "UsageFault", "RESERVED",
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"RESERVED", "RESERVED", "RESERVED", "SVCall",
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"DebugMonitor", "RESERVED", "PendSV", "SysTick"
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};
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char* armv7m_core_reg_list[] =
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@ -54,8 +60,8 @@ char* armv7m_core_reg_list[] =
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12",
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"sp", "lr", "pc",
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"xPSR", "msp", "psp",
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/* Registers accessed through special reg 20 */
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"primask", "basepri", "faultmask", "control"
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/* reg 20 has 4 bytes: CONTROL, FAULTMASK, BASEPRI, PRIMASK */
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"spec20",
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};
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uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
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@ -105,11 +111,11 @@ armv7m_core_reg_t armv7m_core_reg_list_arch_info[] =
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{17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */
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{18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */
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/* CORE_SP are accesible using coreregister 20 */
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{19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */
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{20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */
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{21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */
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{22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */
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/* FIXME the register numbers here are core-specific.
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* Numbers 0..18 above work for all Cortex-M3 revisions.
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* Number 20 below works for CM3 r2p0 and later.
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*/
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{20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL},
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};
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int armv7m_core_reg_arch_type = -1;
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@ -381,12 +387,21 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
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armv7m_set_core_reg(reg, reg_params[i].value);
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}
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if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY)
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/* NOTE: CONTROL is bits 31:24 of SPEC20 register, if it's present;
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* holding a two-bit field.
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*
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* FIXME need a solution using ARMV7M_T_MSR(). Use it at least for
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* earlier cores.
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*/
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if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY
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&& armv7m->has_spec20)
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{
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LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode);
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buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode);
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armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1;
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armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1;
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buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20].value,
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24, 2, armv7m_algorithm_info->core_mode);
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armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1;
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armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1;
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}
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/* ARMV7M always runs in Thumb state */
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@ -61,10 +61,15 @@ enum
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ARMV7M_xPSR = 16,
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ARMV7M_MSP,
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ARMV7M_PSP,
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ARMV7M_PRIMASK,
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ARMV7M_BASEPRI,
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ARMV7M_FAULTMASK,
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ARMV7M_CONTROL,
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/* FIXME the register numbers here are core-specific. Cortex-M3
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* through r1p1 only defines registers up to PSP; see ARM DDI 0337E.
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*
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* It's r2p0 (see ARM DDI 0337G) which defines the register that's
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* called SPEC20 here, with four single-byte fields with CONTROL
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* (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte).
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*/
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ARMV7M_SPEC20 = 20,
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ARMV7NUMCOREREGS
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};
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@ -78,6 +83,7 @@ typedef struct armv7m_common_s
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int exception_number;
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swjdp_common_t swjdp_info;
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bool has_spec20;
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/* Direct processor core register read and writes */
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int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
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@ -24,7 +24,7 @@
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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* *
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* *
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* Cortex-M3(tm) TRM, ARM DDI 0337C *
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* Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
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* *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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@ -395,7 +395,7 @@ int cortex_m3_debug_entry(target_t *target)
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/* Examine target state and mode */
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/* First load register acessible through core debug port*/
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for (i = 0; i < ARMV7M_PRIMASK; i++)
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for (i = 0; i < ARMV7NUMCOREREGS; i++)
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{
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if (!armv7m->core_cache->reg_list[i].valid)
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armv7m->read_core_reg(target, i);
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@ -418,22 +418,19 @@ int cortex_m3_debug_entry(target_t *target)
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cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
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}
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/* Now we can load SP core registers */
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for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++)
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{
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if (!armv7m->core_cache->reg_list[i].valid)
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armv7m->read_core_reg(target, i);
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}
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/* Are we in an exception handler */
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if (xPSR & 0x1FF)
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{
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armv7m->core_mode = ARMV7M_MODE_HANDLER;
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armv7m->exception_number = (xPSR & 0x1FF);
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}
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else
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else if (armv7m->has_spec20)
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{
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armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
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/* NOTE: CONTROL is bits 31:24 of SPEC20 register, holding
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* a two-bit field. Unavailable before r2p0...
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*/
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armv7m->core_mode = buf_get_u32(
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armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, 24, 2);
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armv7m->exception_number = 0;
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}
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@ -636,16 +633,26 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int
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if (debug_execution)
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{
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/* Disable interrupts */
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/* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
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/* We disable interrupts in the PRIMASK register instead
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* of masking with C_MASKINTS,
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* This is probably the same issue as Cortex-M3 Errata 377493:
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* C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
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buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
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armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
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armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
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* C_MASKINTS in parallel with disabled interrupts can cause
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* local faults to not be taken. (FIXED in r1p0 and later.)
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*
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* NOTE: PRIMASK is bits 7:0 of SPEC20 register, holding a
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* one bit field. Available this way for r2p0 and later...
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*/
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if (armv7m->has_spec20) {
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buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20]
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.value, 0, 1, 1);
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armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1;
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armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1;
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}
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/* Make sure we are in Thumb mode */
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buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
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buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
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buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32)
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| (1 << 24));
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armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
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armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
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}
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@ -1467,8 +1474,14 @@ int cortex_m3_examine(struct target_s *target)
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if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK)
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return retval;
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if (((cpuid >> 4) & 0xc3f) == 0xc23)
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if (((cpuid >> 4) & 0xc3f) == 0xc23) {
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LOG_DEBUG("CORTEX-M3 processor detected");
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if (((cpuid >> 20) & 0xf) >= 2) {
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armv7m->has_spec20 = true;
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LOG_DEBUG("r2p0 or later detected");
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}
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} else
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LOG_WARNING("not a CORTEX-M3 processor?");
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LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
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target_read_u32(target, NVIC_ICTR, &ictr);
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@ -117,6 +117,21 @@ extern char* cortex_m3_state_strings[];
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#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
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#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
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/* Use MRS/MSR to read/write any of these special registers. Some of
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* them (xPSR, MSP, PSP) are always available using DCRxR. Starting in
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* Cortex-M3 r2p0, some (CONTROL, BASEPRI, and *MASK) are also available
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* through DCRxR.
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* NOTE: this listing omits xPSR components and other mixtures.
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*/
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#define SR_XPSR 3
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#define SR_MSP 8
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#define SR_PSP 9
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#define SR_PRIMASK 16
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#define SR_BASEPRI 17
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#define SR_BASEPRI_MAX 18
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#define SR_FAULTMASK 19
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#define SR_CONTROL 20
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typedef struct cortex_m3_fp_comparator_s
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{
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int used;
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